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| description the CXD2597Q is a digital signal processor lsi for cd players. this lsi incorporates a digital servo, digital filter, zero detection circuit, 1-bit dac and analog low-pass filter on a single chip. features digital signal processor (dsp) block playback mode supporting cav (constant angular velocity) frame jitter free 0.5 to 4 continuous playback possible allows relative rotational velocity readout ?wide capture range playback mode spindle rotational velocity following method supports normal-speed to 4 speed playback 16k ram efm data demodulation enhanced efm frame sync signal protection sec strategy-based error correction subcode demodulation and sub q data error detection digital spindle servo 16-bit traverse counter asymmetry correction circuit cpu interface on serial bus error correction monitor signal, etc. output from a new cpu interface servo auto sequencer digital audio interface outputs digital level meter, peak meter cd text data demodulation digital servo (dssp) block microcomputer software-based flexible servo control offset cancel function for servo error signal auto gain control function for servo loop e:f balance, focus bias adjustment functions digital filter, dac and analog low-pass filter blocks dbb (digital bass boost) function double-speed playback supported digital de-emphasis digital attenuation zero detection function 8fs oversampling digital filter s/n: 100db or more (master clock: 384fs, typ.) logical value: 109db thd + n: 0.007% or less (master clock: 384fs, typ.) rejection band attenuation: ?0db or less applications cd players structure silicon gate cmos ic absolute maximum ratings supply voltage v dd ?.3 to +7.0 v input voltage v i ?.3 to +7.0 v (v ss ?0.3v to v dd + 0.3) output voltage v o ?.3 to +7.0 v storage temperature tstg ?0 to +125 ? supply voltage difference v ss ?av ss ?.3 to +0.3 v v dd ?av dd ?.3 to +0.3 v note) av dd includes xv dd and av ss includes xv ss . recommended operating conditions supply voltage v dd +2.7 to +5.5 v operating temperature topr ?0 to +75 ? note) the v dd for the CXD2597Q varies according to the playback speed selection. ?1 CXD2597Q e97z35-ps cd digital signal processor with built-in digital servo and dac sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. playback speed cd-dsp block dac block 4 4.75 to 5.25 2 3.0 to 5.5 4.5 to 5.5 2.7 to 5.5 1 2.7 to 5.5 v dd [v] i/o capacitance input capacitance c i 11 (max.) pf output capacitance c o 11 (max.) pf i/o capacitance c i/o 11 (max.) pf note) measurement conditions v dd = v i = 0v f m = 1mhz 80 pin qfp (plastic)
? 2 CXD2597Q block diagram p w m p w m a o u t 1 a i n 1 l o u t 1 a o u t 2 a i n 2 l o u t 2 3 r d - o r d e r n o i s e s h a p e r o v e r s a m p l i n g d i g i t a l f i l t e r s e r i a l - i n i n t e r f a c e l m u t r m u t x t a o x t a i t i m i n g l o g i c x r s t t e s t t e s 1 d / a i n t e r f a c e d o u t e r r o r c o r r e c t o r 1 6 k r a m d i g i t a l o u t s u b c o d e p r o c e s s o r a s y m m e t r y c o r r e c t o r d i g i t a l p l l d i g i t a l c l v c p u i n t e r f a c e s e r v o a u t o s e q u e n c e r s i g n a l p r o c e s s o r b l o c k d a c b l o c k s y s m b c k p c m d l r c k c 2 p o w f c k e m p h g f s x u g f r f a c a s y i a s y o b i a s x p c k f i l o f i l i p c o c l t v m d p l o c k s e n s d a t a x l a t c l o k s p o a s p o b x l o n s c o r s q s o s q c k s e r v o b l o c k s e r v o i n t e r f a c e s c l k c o u t s s t p a t s k m i r r d f c t f o k m i r r d f c t f o k s e r v o d s p f o c u s s e r v o t r a c k i n g s e r v o s l e d s e r v o p w m g e n e r a t o r f o c u s p w m g e n e r a t o r t r a c k i n g p w m g e n e r a t o r s l e d p w m g e n e r a t o r f f d r f r d r t f d r t r d r s f d r s r d r r f d c t e s e f e v c i g e n o p a m p a n a l o g s w a / d c o n v e r t e r c l o c k g e n e r a t o r x t s l v p c o d s c v c t l e f m d e m o d u r a t o r ? 3 CXD2597Q pin configuration 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 l r c k p c m d b c k e m p h x v d d x t a i x t a o x v s s a v d d 1 a o u t 1 a i n 1 l o u t 1 a v s s 1 a v s s 2 l o u t 2 a i n 2 a o u t 2 a v d d 2 r m u t l m u t s e f e v c x t s l t e s 1 t e s t v s s f r d r c o u t f f d r t r d r t f d r s r d r s f d r s s t p m d p l o c k m i r r d o u t v d d v s s t e r f d c f i l i c l t v a v s s 3 a s y o a v d d 0 i g e n a v s s 0 a v d d 3 p c o b i a s a s y i f i l o r f a c s q c k x l a t s e n s d a t a x r s t s y s m c l o k v d d s q s o s c l k s c o r a t s k s p o a s p o b x l o n w f c k x u g f x p c k g f s c 2 p o f o k d f c t v c t l v p c o ? 4 CXD2597Q pin description pin no. symbol i/o description sub q 80-bit, pcm peak and level data outputs. cd text data output. sqso readout clock input. system reset. reset when low. mute input. muted when high. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. sens output to cpu. sens serial data readout clock input. digital power supply. anti-shock input/output. microcomputer extension interface (input a) microcomputer extension interface (input b) microcomputer extension interface (output) wfck output. xugf output. mint1 or rfck is output by switching with the command. xpck output. mnt0 is output by switching with the command. gfs output. mnt3 or xrof is output by switching with the command. c2po output. gtop is output by switching with the command. outputs a high signal when either subcode sync s0 or s1 is detected. track count signal input/output. mirror signal input/output. defect signal input/output. focus ok signal input/output. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. or input when lkin = 1. spindle motor servo control output. disc innermost track detection signal input. sled drive output. sled drive output. tracking drive output. tracking drive output. focus drive output. focus drive output. digital gnd. test pin. normally, gnd. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 o i i i i i i o i i/o i i o o o o o o o i/o i/o i/o i/o i/o o i o o o o o o i sqso sqck xrst sysm data xlat clok sens sclk v dd atsk spoa spob xlon wfck xugf xpck gfs c2po scor cout mirr dfct fok lock mdp sstp sfdr srdr tfdr trdr ffdr frdr v ss test 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 ? 5 CXD2597Q pin no. symbol i/o description test pin. normally, gnd. crystal selection input. low when the crystal is 16.9344mhz; high when the crystal is 33.8688mhz. center voltage input. focus error signal input. sled error signal input. tracking error signal input. rf signal input. analog gnd. operational amplifier constant current input. analog power supply. efm full-swing output. (low = vss, high = v dd ) asymmetry comparator voltage input. asymmetry circuit constant current input. efm signal input. analog gnd. multiplier vco1 control voltage input. master pll filter output. (slave = digital pll) master pll filter input. master pll charge pump output. analog power supply. wide-band efm pll vco2 control voltage input. wide-band efm pll charge pump output. digital gnd. digital power supply. digital out output. d/a interface. lr clock output f = fs. d/a interface. serial data output. (two's complement, msb first) d/a interface. bit clock output. outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. master clock power supply. crystal oscillation circuit input. master clock is externally input from this pin. crystal oscillation circuit output. master clock gnd. analog power supply. l ch analog output. l ch operational amplifier input. 1, 0 analog 1, z, 0 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 i i i i i i i i o i i i i o i o i o o o o o o i o o i tes1 xtsl vc fe se te rfdc av ss 0 igen av dd 0 asyo asyi bias rfac av ss 3 cltv filo fili pco av dd 3 vctl vpco v ss v dd dout lrck pcmd bck emph xv dd xtai xtao xv ss av dd 1 aout1 ain1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ? 6 CXD2597Q pin no. symbol i/o description l ch line output. analog gnd. analog gnd. r ch line output. r ch operational amplifier output. r ch analog output. analog power supply. r ch zero detection flag. l ch zero detection flag. 1, 0 1, 0 o o i o o o lout1 av ss 1 av ss 2 lout2 ain2 aout2 av dd 2 rmut lmut 72 73 74 75 76 77 78 79 80 notes) pcmd is a msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window opens.) xugf is the frame sync obtained from the efm signal, and is negative pulse. it is the signal before sync protection. xpck is the inverse of the efm pll clock. the pll is designed so that the falling edge and the efm signal transition point coincide. the gfs signal goes high when the frame sync and the insertion protection timing match. rfck is derived from the crystal accuracy, and has a cycle of 136 s. c2po represents the data error status. xrof is generated when the 16k ram exceeds the 4f jitter margin. monitor pin output combinations command bit output data mtsl1 0 0 1 0 1 0 xugf mnt1 rfck xpck mnt0 xpck gfs mnt3 xrof c2po c2po gtop mtsl0 ? 7 CXD2597Q electrical characteristics 1. dc characteristics (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75 c) item input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (3) input leak current (1) input leak current (2) input leak current (3) input leak current (4) * 1 , * 9 * 2 , * 10 * 3 , * 7 , * 8 * 4 * 5 * 6 * 1 , * 2 * 9 , * 10 * 7 * 8 schmitt input analog input i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i oh = 0.28ma i ol = 0.36ma v in = v ss or v dd v in = v ss or v dd v i = 1.5 to 3.5v v i = 0 to 5.0v high level input voltage low level input voltage high level input voltage low level input voltage input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage v i h (1) v il (1) v ih (2) v i l (2) v i n (3) v o h (1) v ol (1) v oh (2) v ol (2) v oh (3) v ol (3) i li (1) i li (2) i li (3) i li (4) 0.7v dd 0.8v dd vss v dd ?0.8 vss v dd ?0.8 vss v dd ?0.5 vss ?0 ?0 ?0 ?0 0.3v dd 0.2v dd v dd v dd 0.4 v dd 0.4 v dd 0.4 10 40 20 600 v v v v v v v v v v v a a a a conditions min. typ. max. unit applicable pins applicable pins * 1 sysm, data, xlat, sstp, xtsl, test, tes1 * 2 sqck, xrst, clok * 3 asyi, rfac, cltv, fili, vctl * 4 sqso, sens, atsk, xlon, wfck, xugf, xpck, gfs, c2po, scor, cout, mirr, dfct, fok, lock, sfdr, srdr, tfdr, trdr, ffdr, frdr, asyo, dout, lrck, pcmd, bck, emph, rmut, lmut * 5 mdp, pco, vpco * 6 filo * 7 vc, fe, se, te * 8 rfdc * 9 atsk, cout, mirr, dfct, fok, lock * 10 sclk, spoa, spob ? 8 CXD2597Q 2. ac characteristics (1) xtai pin (a) when using self-excited oscillation (topr = ?0 to +75 c, v dd = av dd = 5.0v 5%) (b) when inputting pulses to xtai pin (topr = ?0 to +75 c, v dd = av dd = 5.0v 5%) (c) when inputting sine waves to xtai pin via a capacitor (topr = ?0 to +75 c, v dd = av dd = 5.0v 5%) oscillation frequency f max 7 34 mhz item symbol min. typ. max. unit high level pulse width t whx 13 500 ns low level pulse width t wlx 13 500 ns pulse cycle t ck 26 1,000 ns input high level v ihx v dd ?1.0 v input low level v ilx 0.8 v rise time, fall time t r , t f 10 ns item symbol min. typ. max. unit input amplitude v i 2.0 v dd + 0.3 vp-p item symbol min. typ. max. unit t r t f t w h x t w l x t c x v i l x v i h x 0 . 1 v i h x 0 . 9 v i h x x t a i v d d / 2 ? 9 CXD2597Q (2) clok, data, xlat and sqck pin (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75 c) clock frequency clock pulse width setup time hold time delay time latch pulse width sqck frequency sqck pulse width f ck t wck t su t h t d t wl f t t wt 750 300 300 300 750 750 note) 0.65 0.65 note) mhz ns ns ns ns ns mhz ns item symbol min. typ. max. unit t w c k t w c k 1 / f c k t h t s u t w l t d 1 / f t t w t t w t t h t s u c l o k d a t a x l a t s q c k s q s o note) in quasi double-speed playback mode, except when sqso is sub q read, the sqck maximum operating frequency is 300khz and its minimum pulse width is 1.5 s. ? 10 CXD2597Q (4) cout, mirr and dfct pins operating frequency (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75 c) cout maximum operating frequency mirr maximum operating frequency dfct maximum operating frequency f cout f mirr f dfcth 40 40 5 khz khz khz * 1 * 2 * 3 item symbol min. typ. max. unit conditions * 1 when using a high-speed traverse tzc. * 2 when the rf signal continuously satisfies the following conditions during the above traverse. a = 0.12v dd to 0.26v dd 25% * 3 during complete rf signal omission. when settings related to dfct signal generation are typ. (3) sclk pin sclk frequency sclk pulse width delay time f sclk t spw t dls 31.3 15 16 mhz ns s item symbol min. typ. max. unit t s p w t d l s 1 / f s c l k m s b l s b x l a t s c l k s e r i a l r e a d o u t d a t a ( s e n s ) a b b a + b ? 11 CXD2597Q 1-bit dac and lpf block analog characteristics analog characteristics (v dd = av dd = 5.0v, v ss = av ss = 0v, ta = 25 c) fs = 44.1khz in all cases. the total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. lpf external circuit diagram block diagram of analog characteristics measurement item total harmonic distortion signal-to-noise ratio symbol thd s/n conditions 1khz, 0db data crystal 1khz, 0db data (using a-weighting filter) 384fs 768fs 384fs 768fs 96 96 0.0050 0.0045 100 100 0.0070 0.0065 min. typ. max. unit % db a u d i o a n a l y z e r s h i b a s o k u ( a m 5 1 a ) 1 0 0 k 2 2 6 8 0 p 1 2 k 1 2 k 1 2 k 1 5 0 p a o u t 1 ( 2 ) a i n 1 ( 2 ) l o u t 1 ( 2 ) a u d i o a n a l y z e r c x d 2 5 9 7 q r c h a l c h b d a t a r f t e s t d i s c 7 6 8 f s / 3 8 4 f s (v dd = av dd = 5.0v, v ss = av ss = 0v, topr = ?0 to +75 c) output voltage load resistance v out r l * 1 * 1 vrms k item symbol 8 min. max. 1.12 typ. applicable pins unit * measurement is conducted for the lpf external circuit diagram with the sine wave output of 1khz and 0db. applicable pins * 1 lout1, lout2 ? 12 CXD2597Q contents ?. cpu interface ?-1. cpu interface timing ........................................................................................................................ 13 ?-2. cpu interface command table ........................................................................................................ 13 ?-3. cpu command presets .................................................................................................................... 23 ?-4. description of sens signals and commands ................................................................................... 28 ?. subcode interface ?-1. 80-bit sub q readout ........................................................................................................................ 47 ?. description of modes ?-1. clv-n mode ............................................................................................................................... ....... 51 ?-2. clv-w mode ............................................................................................................................... ...... 51 ?-3. cav-w mode ............................................................................................................................... ...... 51 ?. description of other functions ?-1. channel clock recovery by digital pll circuit ................................................................................. 53 ?-2. frame sync protection ...................................................................................................................... 55 ?-3. error correction ............................................................................................................................... .. 55 ?-4. da interface ............................................................................................................................... ........ 56 ?-5. digital out ............................................................................................................................... ........... 58 ?-6. servo auto sequence ....................................................................................................................... 58 ?-7. digital clv ............................................................................................................................... .......... 65 ?-8. cd-dsp block playback speed ........................................................................................................ 66 ?-9. dac block playback speed .............................................................................................................. 66 ?-10. description of dac block functions .................................................................................................. 67 ?-11. lpf block ............................................................................................................................... ........... 70 ?-12. asymmetry correction ....................................................................................................................... 71 ?-13. cd text data demodulation ........................................................................................................... 72 ?. description of servo signal processing system functions and commands ?-1. general description of servo signal processing system .................................................................. 74 ?-2. digital servo block master clock (mck) ........................................................................................... 75 ?-3. avrg measurement and compensation .......................................................................................... 75 ?-4. e:f balance adjustment function ..................................................................................................... 77 ?-5. fcs bias adjustment function .......................................................................................................... 77 ?-6. agcntl function ............................................................................................................................. 79 ?-7. fcs servo and fcs search ............................................................................................................. 81 ?-8. trk and sld servo control ............................................................................................................. 82 ?-9. mirr and dfct signal generation .................................................................................................. 83 ?-10. dfct countermeasure circuit .......................................................................................................... 84 ?-11. anti-shock circuit .............................................................................................................................. 84 ?-12. brake circuit ............................................................................................................................... ....... 85 ?-13. cout signal ............................................................................................................................... ...... 86 ?-14. serial readout circuit ........................................................................................................................ 86 ?-15. writing to coefficient ram ................................................................................................................ 87 ?-16. pwm output ............................................................................................................................... ....... 87 ?-17. servo status changes produced by lock signal ........................................................................... 89 ?-18. description of commands and data sets ......................................................................................... 89 ?-19. list of servo filter coefficients ........................................................................................................ 104 ?-20. filter composition ............................................................................................................................ 106 ?-21. tracking and focus frequency response .............................................................................. 113 ?. application circuit ............................................................................................................................... ... 114 explanation of abbreviations avrg: average agcntl: auto gain control fcs: focus trk: tracking sld: sled dfct: defect ? 13 CXD2597Q ?. cpu interface ?-1. cpu interface timing cpu interface this interface uses data, clok and xlat to set the modes. the interface timing chart is shown below. the internal registers are initialized by a reset when xrst = 0. note) be sure to set sqck to high when xlat is low. ?-2. cpu interface command table total bit length for each register register 0 to 2 3 4 to 6 7 8 9 a b c d e 8 bits 8 to 24 bits 8 bits 20 bits 28 bits 24 bits 28 bits 16 bits 8 bits 16 bits 20 bits total bit length 7 5 0 n s o r m o r e d 1 8 d 1 9 d 2 0 d 2 1 d 2 2 d 2 3 7 5 0 n s o r m o r e v a l i d c l o k d a t a x l a t r e g i s t e r s d 0 d 1 ? 14 CXD2597Q command table ($0x to 1x) focus servo on (focus gain normal) focus servo on (focus gain down) focus servo off, 0v out focus servo off, focus search voltage out focus search voltage down focus seach voltage up anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 1 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 focus control tracking control register command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 ? don? care ? 15 CXD2597Q command table ($2x to 3x) tracking servo off tracking servo on forward track jump reverse track jump sled servo off sled servo on forward sled move reverse sled move sled kick level ( 1 basic value) (default) sled kick level ( 2 basic value) sled kick level ( 3 basic value) sled kick level ( 4 basic value) 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 2 3 0 0 1 0 0 0 1 1 tracking mode select register command address d23 to d20 register command address d23 to d20 data 1 d19 d18 d17 d16 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 ? don? care ? 16 CXD2597Q command table ($340x) kram data (k00) sled input gain kram data (k01) sled low boost filter a-h kram data (k02) sled low boost filter a-l kram data (k03) sled low boost filter b-h kram data (k04) sled low boost filter b-l kram data (k05) sled output gain kram data (k06) focus input gain kram data (k07) sled auto gain kram data (k08) focus high cut filter a kram data (k09) focus high cut filter b kram data (k0a) focus low boost filter a-h kram data (k0b) focus low boost filter a-l kram data (k0c) focus low boost filter b-h kram data (k0d) focus low boost filter b-l kram data (k0e) focus phase compensate filter a kram data (k0f) focus defect hold gain 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 ? 17 CXD2597Q command table ($341x) kram data (k10) focus phase compensate filter b kram data (k11) focus output gain kram data (k12) anti shock input gain kram data (k13) focus auto gain kram data (k14) hptzc / auto gain high pass filter a kram data (k15) hptzc / auto gain high pass filter b kram data (k16) anti shock high pass filter a kram data (k17) hptzc / auto gain low pass filter b kram data (k18) fix kram data (k19) tracking input gain kram data (k1a) tracking high cut filter a kram data (k1b) tracking high cut filter b kram data (k1c) tracking low boost filter a-h kram data (k1d) tracking low boost filter a-l kram data (k1e) tracking low boost filter b-h kram data (k1f) tracking low boost filter b-l 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 1 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 ? 18 CXD2597Q command table ($342x) kram data (k20) tracking phase compensate filter a kram data (k21) tracking phase compensate filter b kram data (k22) tracking output gain kram data (k23) tracking auto gain kram data (k24) focus gain down high cut filter a kram data (k25) focus gain down high cut filter b kram data (k26) focus gain down low boost filter a-h kram data (k27) focus gain down low boost filter a-l kram data (k28) focus gain down low boost filter b-h kram data (k29) focus gain down low boost filter b-l kram data (k2a) focus gain down phase compensate filter a kram data (k2b) focus gain down defect hold gain kram data (k2c) focus gain down phase compensate filter b kram data (k2d) focus gain down output gain kram data (k2e) not used kram data (k2f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 ? 19 CXD2597Q command table ($343x) kram data (k30) sled input gain (when sfsk = 1 tg up2) kram data (k31) anti shock low pass filter b kram data (k32) not used kram data (k33) anti shock high pass filter b-h kram data (k34) anti shock high pass filter b-l kram data (k35) anti shock filter comparate gain kram data (k36) tracking gain up2 high cut filter a kram data (k37) tracking gain up2 high cut filter b kram data (k38) tracking gain up2 low boost filter a-h kram data (k39) tracking gain up2 low boost filter a-l kram data (k3a) tracking gain up2 low boost filter b-h kram data (k3b) tracking gain up2 low boost filter b-l kram data (k3c) tracking gain up phase compensate filter a kram data (k3d) tracking gain up phase compensate filter b kram data (k3e) tracking gain up output gain kram data (k3f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 1 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 ? 20 CXD2597Q command table ($344x) kram data (k40) tracking hold filter input gain kram data (k41) tracking hold filter a-h kram data (k42) tracking hold filter a-l kram data (k43) tracking hold filter b-h kram data (k44) tracking hold filter b-l kram data (k45) tracking hold filter output gain kram data (k46) tracking hold input gain (when thsk = 1 tg up2) kram data (k47) not used kram data (k48) focus hold filter input gain kram data (k49) focus hold filter a-h kram data (k4a) focus hold filter a-l kram data (k4b) focus hold filter b-h kram data (k4c) focus hold filter b-l kram data (k4d) focus hold filter output gain kram data (k4e) not used kram data (k4f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 1 0 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 ? 21 CXD2597Q command table ($34fx to 3fx) 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage/auto gain dtzc/track jump voltage/auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc/cout bottom/mirr sled filter filter others 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 fbl9 fb9 tv9 fbl8 fb8 tv8 fbl7 fb7 tv7 fbl6 fb6 tv6 fbl5 fb5 tv5 fbl4 fb4 tv4 fbl3 fb3 tv3 fbl2 fb2 tv2 fbl1 fb1 tv1 tv0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 ft1 tdzc fzsh vclm dac 0 sfo2 ft0 dtzc fzsl vclc sd6 fbon sfo1 fs5 tj5 sm5 flm sd5 fbss sdf2 fs4 tj4 sm4 flc0 sd4 fbup sdf1 fs3 tj3 sm3 rflm sd3 fbv1 max2 fs2 tj2 sm2 rflc sd2 fbv0 max1 fs1 tj1 sm1 agf sd1 0 sfox fs0 tj0 sm0 agt sd0 tjd0 btf ftz sfjp ags dfsw 0 fps1 d2v2 fg6 tg6 agj lksw 0 fps0 d2v1 fg5 tg5 aggf tblm 0 tps1 d1v2 fg4 tg4 aggt tclm 0 tps0 d1v1 fg3 tg3 agv1 flc1 0 0 rint fg2 tg2 agv2 tlc2 0 sjhd 0 fg1 tg1 aghs tlc1 0 inbk 0 fg0 tg0 aght tlc0 0 mti0 0 1 1 1 1 1 1 1 1 0 1 f1nm 0 f1dm agg4 f3nm xt4d f3dm xt2d t1nm 0 t1um drr2 t3nm drr1 t3um drr0 dfis 0 tlcd asfg 0 ftq lkin lpas coin sro1 mdfi 0 miri aghf xt1d asot 1 1 0 0 0 1 coss sfid cots sfsk 0 thid 0 thsk cot2 0 cot1 tld2 mot2 tld1 0 tld0 bts1 0 bts0 0 mrc1 0 mrc0 0 0 0 0 0 0 0 0 0 select register command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 ? don? care ? 22 CXD2597Q instruction table register 4 5 6 7 8 9 a b c d e auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl spindle servo coefficient setting clv ctrl clv mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 2048 vco sel1 0 0 0 0 trmi vp7 epwm 1024 0 0 0 0 0 trmo vp6 spdc 512 soct 0 0 opsl2 0 opsl2 1 mtsl1 vp5 icap 256 vco sel2 0 0 emph emph mtsl0 vp4 sfsl 128 ksl3 opsl1 0 opsl1 1 smut smut 0 vp3 vc2c 64 ksl2 mcsl mcsl 0 0 0 vp2 hifc 32 ksl1 0 0 ad9 ad9 0 vp1 lpwr 16 ksl0 0 0 ad8 ad8 0 vp0 vpon 8 0 zdpl zdpl ad7 ad7 gain cav1 4 0 zmut zmut ad6 ad6 gain cav0 2 0 0 ad5 ad5 0 1 0 0 ad4 ad4 0 0 0 ad3 ad3 0 dcof ad2 ad2 0 0 ad1 ad1 0 0 ad0 ad0 txon fmut txout lrwo outl1 bsbst outl0 bbsl as3 0.18ms 0.36ms 11.6ms 32768 cdrom 0 0 0 0 sl1 gain mdp1 0 cm3 as2 0.09ms 0.18ms 5.8ms 16384 dout mute dspb on/off dspb on/off 0 0 sl0 gain mdp0 tb cm2 as1 0.05ms 0.09ms 2.9ms 8192 dout on/off 0 0 mute mute cpusr gain mds1 tp cm1 as0 0.02ms 0.05ms 1.45ms 4096 wsel 0 0 att att 0 gain mds0 gain clvs cm0 command address d3 d2 d1 d0 data 1 d3 d2 d1 d0 data 2 d3 d2 d1 d0 data 3 d3 d2 d1 d0 data 4 d3 d2 d1 d0 data 5 d3 d2 d1 d0 data 6 d3 d2 d1 d0 ? 23 CXD2597Q focus servo off, 0v out tracking gain up filter select 1 tracking servo off sled servo off sled kick level ( 1 basic value) (default) kram data ($3400xx to $344fxx) 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 0 0 0 0 0 1 0 0 1 0 focus control tracking control tracking mode register command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 register command 3 select address d23 to d20 0 0 1 1 0 0 1 1 0 1 0 0 0 see "coefficient rom preset values table". 0 0 0 0 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d0 d0 address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 address 3 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d0 d0 ?-3. cpu command presets command preset table ($0x to 34x) ? don? care ? 24 CXD2597Q command preset table ($34fx to 3fx) 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage auto gain dtzc/track jump voltage auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc/cout bottom/mirr sled filter 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 filter others 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 select register command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 ? don? care ? 25 CXD2597Q reset initialization register 4 5 6 7 8 9 a b c d e auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl spindle servo coefficient setting clv ctrl clv mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 command address d3 d2 d1 d0 data 1 d3 d2 d1 d0 data 2 d3 d2 d1 d0 data 3 d3 d2 d1 d0 data 4 d3 d2 d1 d0 data 5 d3 d2 d1 d0 data 6 d3 d2 d1 d0 ? 26 CXD2597Q ? 27 CXD2597Q ? 28 CXD2597Q ?-4. description of sens signals and commands sens output the sens output can be read from the sqso pin when soct = 0, sl1 = 1 and sl0 = 0. (see $bx commands.) $38 outputs agok during agt and agf command settings, and xavebsy during avrg measurement. sstp is output in all other cases. microcomputer serial register (latching not required) $0x $1x $2x $30 to 37 $38 $38 $3904 $3908 $390c $391c $391d $391f $3a $3b to 3f $4x $5x $6x, 7x, 8x, 9x $ax $bx $cx $dx $ex $fx sens output fzc as (anti shock) tzc sstp agok xa vebsy te avrg reg. fe avrg reg. vc avrg reg. trvsc reg. fb reg. rfdc avrg. reg. fbias count stop sstp xbusy fok 0 gfs 0 cout frequency division 0 ov64 0 output data length 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits description of sens signals low while the auto sequencer is in operation, high when operation terminates. outputs the same signal as the fok pin. high for "focus ok". high when the regenerated frame sync is obtained with the correct timing. counts the number of tracks with frequency division ratio set by $b. high when $c is latched, and toggles each time cout is counted just for the frequency division ratio set by $b. low when the efm signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. xbusy fok gfs cout frequency division ov64 sens output contents ? 29 CXD2597Q the meaning of the data for each address is explained below. $4x commands rxf = 0 forward rxf = 1 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump/move commands ($48 to $4f) are canceled, $25 is sent and the auto sequence is interrupted. $5x commands auto sequence timer setting set timers: a, e, c, b e.g.) d2 = d0 = 1, d3 = d1 = 0 (initial reset) a = e = c = 0.11ms b = 0.23ms $6x commands auto sequence timer setting set timer: d e.g.) d3 = 0, d2 = d1 = d0 = 1 (initial reset) d = 10.15ms $7x commands auto sequence track jump/move count setting (n) this command is used to set n when a 2n-track jump or n-track move is executed for auto sequence. the maximum track count is 65,535, but note that with a 2n-track jump the maximum track jump count depends on the mechanical limitations of the optical system. the number of tracks jumped is counted according to the cout signals. cancel focus-on 1 track jump 10 track jump 2 ntrack jump n track move 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 rxf rxf rxf rxf command as3 as2 as1 as0 blind (a, e), over flow (c) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.05ms 0.09ms 0.02ms 0.05ms command d3 d2 d1 d0 kick (d) 11.6ms 5.8ms 2.9ms 1.45ms command command data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump count setting d3 d2 d1 d0 ? 30 CXD2597Q command bit c2po timing cdrom = 1 cdrom = 0 see timing chart 1-1. see timing chart 1-1. cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing command bit dout mute = 1 dout mute = 0 digital out output is muted. (da output is not muted.) if other mute conditions are not set, digital out is not muted. processing command bit dout on/off = 1 dout on/off = 0 digital out is output from the dout pin. digital out is not output from the dout pin. processing command bit sync protection window width wsel = 1 wsel = 0 26 channel clock * 1 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application * 1 in normal-speed playback, channel clock = 4.3218mhz. command d3 cdrom dout mute dout on/off wsel vco sel1 0 soct vco sel2 ksl3 ksl2 ksl1 ksl0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 mode specification data 3 d3 0 0 0 0 0 0 0 0 txon txout outl1 outl0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 4 data 5 data 6 $8x commands see "$bx commands". ? 31 CXD2597Q command bit vcosel1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 multiplier pll vco1 is set to normal speed, and the output is 1/1 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/2 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/4 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/8 frequency-divided. multiplier pll vco1 is set to high speed * 1 , and the output is 1/1 frequency-divided. multiplier pll vco1 is set to high speed * 1 , and the output is 1/2 frequency-divided. multiplier pll vco1 is set to high speed * 1 , and the output is 1/4 frequency-divided. multiplier pll vco1 is set to high speed * 1 , and the output is 1/8 frequency-divided. ksl3 ksl2 processing * 1 approximately twice the normal speed command bit vcosel2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 wide-band pll vco2 is set to normal speed, and the output is 1/1 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/2 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/4 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/8 frequency-divided. wide-band pll vco2 is set to high speed * 2 , and the output is 1/1 frequency-divided. wide-band pll vco2 is set to high speed * 2 , and the output is 1/2 frequency-divided. wide-band pll vco2 is set to high speed * 2 , and the output is 1/4 frequency-divided. wide-band pll vco2 is set to high speed * 2 , and the output is 1/8 frequency-divided. ksl1 ksl0 processing * 2 approximately twice the normal speed ? 32 CXD2597Q command bit txon = 0 processing when cd text data is not demodulated, set txon to 0. when cd text data is demodulated, set txon to 1. * see "$4-13. cd text data demodulation" txon = 1 command bit txout = 0 processing various signals except for cd text is output from the sqso pin. cd text data is output from the sqso pin. * see "$4-13. cd text data demodulation" txout = 1 command bit outl1 = 0 processing wfck and xpck are output. wfck and xpck outputs are set to low. outl1 = 1 command bit outl0 = 0 outl0 = 1 processing pcmd, bck, lrck and emph are output. pcmd, bck, lrck and emph outputs are low. ? 33 CXD2597Q timing chart 1-1 r c h 1 6 b i t c 2 p o i n t e r l c h 1 6 b i t c 2 p o i n t e r i f c 2 p o i n t e r = 1 , d a t a i s n g c 2 p o i n t e r f o r u p p e r 8 b i t s c 2 p o i n t e r f o r l o w e r 8 b i t s r c h c 2 p o i n t e r c 2 p o i n t e r f o r u p p e r 8 b i t s c 2 p o i n t e r f o r l o w e r 8 b i t s l c h c 2 p o i n t e r l r c k c d r o m = 0 c d r o m = 1 c 2 p o c 2 p o ? 34 CXD2597Q command bit zdpl = 1 zdpl = 0 lmut and rmut pins are high when muted. lmut and rmut pins are low when muted. processing * see "mute flag output" for the mute flag output conditions. $9x commands (opsl1= 0) * data 2 d0 and subsequent data are for df/dac function settings. command bit dspb = 1 dspb = 0 double-speed playback (cd-dsp block) normal-speed playback (cd-dsp block) processing command bit opsl1 = 1 opsl1 = 0 dcof can be set. dcof cannot be set. processing command bit mcsl = 1 mcsl = 0 df/dac block master clock selection. crystal = 768fs (33.8688mhz) df/dac block master clock selection. crystal = 384fs (16.9344mhz) processing command data 1 d3 0 dspb on/off 0 0 0 mcsl 0 0 zdpl zmut d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 3 data 4 data 2 function specification 000 0 d3 to d1 d0 opsl1 d3 d2 d1 d0 data 5 $9x commands (opsl1= 1) * data 2 d0 and subsequent data are for df/dac function settings. command data 1 d3 0 dspb on/off 0 0 1 mcsl 0 0 zdpl zmut 0 0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 3 data 4 data 2 function specification 000 0 d3 to d1 d0 opsl1 d3 0 dcof 0 0 d2 d1 d0 data 5 ? 35 CXD2597Q command bit dcof = 1 dcof = 0 dc offset is off. dc offset is on. processing * dcof can be set when opsl1 = 1. * set dc offset to off when zero detection mute is on. command bit zmut = 1 zmut = 0 zero detection mute is on. zero detection mute is off. processing $ax commands (opsl2 = 0) * data 2 and subsequent data are for df/dac function settings. command data 1 d3 0 0 mute att 0 0 0 emph d2 d1 d0 d3 d2 d1 d0 data 2 data 3 audio ctrl smut ad10 d3 d2 opsl2 data 4 d3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 data 3 ad9 ad8 d1 d0 $ax commands (opsl2 = 1) * data 2 and subsequent data are for df/dac function settings. command data 1 d3 0 0 mute att 0 0 1 emph d2 d1 d0 d3 d2 d1 d0 data 2 data 3 audio ctrl smut 0 d3 d2 opsl2 data 4 d3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 fmut lrwo bsbst bbsl d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 data 3 ad9 ad8 d1 d0 command bit mute = 1 mute = 0 cd-dsp block mute is on. 0 data is output from the cd-dsp block. cd-dsp block mute is off. processing ? 36 CXD2597Q command bit fmut = 1 fmut = 0 forced mute is on. forced mute is off. meaning * fmut can be set when opsl2 = 1. the attenuation data consists of 11 bits, and is set as follows. attenuation data 400h 3feh 3fdh : 001h 000h 0db ?.0085db ?.0170db ?0.206db ? audio output command bit emph = 1 emph = 0 de-emphasis is on. de-emphasis is off. processing * if either the emphi pin or emph is high, de-emphasis is on. * if either the smut pin or smut is high, soft mute is on. command bit smut = 1 smut = 0 soft mute is on. soft mute is off. processing command bit ad10 to 0 attenuation data. meaning command bit att = 1 att = 0 cd-dsp block output is attenuated (?2db). cd-dsp block output attenuation is off. processing command bit opsl2 = 1 opsl2 = 0 fmut, lrwo, bsbst and bbsl can be set. fmut, lrwo, bsbst and bbsl cannot be set. meaning the attenuation data (ad10 to ad0) consists of 11 bits, and can be set in 1024 different ways in the range of 000h to 400h. the audio output from 001h to 400h is obtained using the following equation. audio output = 20log [db] attenuation data 1024 ? 37 CXD2597Q command bit bsbst = 1 bsbst = 0 bass boost is on. bass boost is off. processing * bsbst can be set when opsl2 = 1. command bit bbsl = 1 bbsl = 0 bass boost is max. bass boost is mid. processing * bbsl can be set when opsl2 = 1. command bit lrwo = 1 lrwo = 0 forced synchronization mode note ) normal operation. meaning * lrwo can be set when opsl2 = 1. note) synchronization is performed at the first falling edge of lrck during reset, so there is normally no need to set this mode. however, synchronization can be forcibly performed by setting lrwo = 1. ? 38 CXD2597Q command d3 sl1 sl0 cpusr 0 d2 d1 d0 trm1 d3 trm0 d2 mtsl1 d1 mtsl0 d0 data 1 data 2 serial bus ctrl $bx commands soct 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 subq peak meter sens d subq a b c sl1 sl0 mode the sqso pin output can be switched to the various signals by setting the soct command of $8x and the sl1 and sl0 commands of $bx. set sqck to high at the falling edge of xlat. except for sub q and peak meter, the signals are loaded to the register when they are set at the falling edge of xlat. sub q is loaded to the register with each scor, and peak meter is loaded when a peak is detected. m o d e a x l a t s q c k m o d e b m o d e c m o d e d p e a k m e t e r p e r 1 p e r 2 p e r 3 p e r 4 p e r 5 p e r 6 p e r 7 c 1 f 1 0 c 1 f 2 c 2 f 1 0 c 2 f 2 f o k l o c k g f s e m p h v f 0 a l o c k v f 1 v f 2 v f 3 v f 4 v f 5 v f 6 v f 7 v f 0 v f 1 v f 2 v f 3 v f 4 v f 5 v f 6 v f 7 a l o c k c 1 f 1 c 1 f 2 0 c 2 f 1 0 c 2 f 2 f o k l o c k g f s e m p h p e r 1 p e r 2 p e r 3 p e r 4 p e r 5 p e r 6 p e r 7 p e r 0 c 1 f 1 c 1 f 2 0 c 2 f 1 0 c 2 f 2 f o k l o c k g f s e m p h 0 p e r 0 s p o a c 1 f 1 c 1 f 2 c 2 f 1 c 2 f 2 x r a o f f o k g f s l 0 l 1 l 2 l 3 l 4 l 5 l 6 l 7 r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 l o c k e m p h r f c k w f c k s c o r 0 0 s p o b g t o p ? 39 CXD2597Q signal per0 to 7 fok gfs lock emph alock vf0 to 7 spoa, b wfck scor gtop rfck xraof l0 to l7, r0 to r7 rf jitter amount (used to adjust the focus bias). 8-bit binary data in per0 = lsb, per7 = msb. focus ok high when the frame sync and the insertion protection timing match. gfs is sampled at 460hz; when gfs is high, a high signal is output. if gfs is low eight consecutive samples, a low signal is output. high when the playback disc has emphasis. gfs is sampled at 460hz; when gfs is high eight consecutive samples, a high signal is output. if gfs is low eight consecutive samples, a low signal is output. used in cav-w mode. results of measuring the disc rotational velocity. (see timing chart 2-3.) vf0 = lsb, vf7 = msb. spoa and b pin inputs. write frame clock output. high when either subcode sync s0 or s1 is detected. high when the sync protection window is open. read frame clock output. low when the built-in 16k ram exceeds the 4 frame jitter margin. peak meter register output. l0 to l7 are the left-channel and r0 to r7 are the right-channel peak data. l0 and r0 are lsb. description c1f1 0 1 1 0 0 1 no error single error correction irretrievable error c1f2 c1 correction status c2f1 0 1 1 0 0 1 no error single error correction irretrievable error c2f2 c2 correction status command bit cpusr = 1 cpusr = 0 xlon pin is high. xlon pin is low. processing ? 40 CXD2597Q peak meter s q s o x l a t s q c k ( p e a k m e t e r ) l 0 l 1 l 2 l 3 l 4 l 5 l 6 l 7 r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 setting the soct command of $8x to 0 and the sl1 and sl0 commands of $bx to 0 and 1, respectively, results in peak detection mode. the sqso output is connected to the peak register. the maximum pcm data values (absolute value, upper 8 bits) for the left and right channels can be read from sqso by inputting 16 clocks to sqck. peak detection is not performed during sqck input, and the peak register does not change during readout. this sqck input judgment uses a retriggerable monostable multivibrator with a time constant of 270 s to 400 s. the time during which sqck input is high should be 270 s or less. also, peak detection is restarted 270 s to 400 s after sqck input. the peak register is reset with each readout (16 clocks input to sqck). the maximum value in peak detection mode is detected and held in this status until the next readout. when switching to peak detection mode, readout should be performed one time initially to reset the peak register. peak detection can also be performed for previous value hold and average value interpolation data. traverse monitor count value setting these bits are set when monitoring the traverse condition of the sens output according to the cout frequency division. command bit 0 0 1 1 0 1 0 1 1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division trm1 xugf mnt1 rfck xugf xpck mnt0 xpck xpck gfs mnt3 xrof gfs c2po c2po gtop c2po mtsl1 0 0 1 command bit mtsl0 0 1 0 symbol trm0 processing output data monitor output switching the monitor output can be switched to the various signals by setting the mtsl1 and mtsl0 commands of $b. ? 41 CXD2597Q $cx commands clv mode gain setting: gclvs clvp mode gain setting: gmdp: gmds servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs ?2db ?db ?db 0db 0db +6db command d3 d2 d1 d0 gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp ?db 0db +6db gain mds1 0 0 1 gain mds0 0 1 0 gmds ?db 0db +6db ? 42 CXD2597Q $dx commands command bit description tb = 0 tb = 1 tp = 0 tp = 1 bottom hold at a cycle of rfck/32 in clvs mode. bottom hold at a cycle of rfck/16 in clvs mode. peak hold at a cycle of rfck/4 in clvs mode. peak hold at a cycle of rfck/2 in clvs mode. command d3 0 tb tp gain clvs vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 clv ctrl data 3 see the $cx commands. the rotational velocity r of the spindle can be expressed with the following equation. r = 32 256 ?n r: relative velocity at normal speed = 1 n: vp0 to vp7 setting value note) values in parentheses are for when dspb is 1. values when crystal is 16.9344mhz and xtsl is low or when crystal is 33.8688mhz and xtsl is high. vp0 to vp7 setting values are valid in cav-w mode. 2 r r e l a t i v e v e l o c i t y [ m u l t i p l e ] 1 . 5 1 0 . 5 f 0 e 0 v p 0 t o v p 7 s e t t i n g v a l u e [ h e x ] d s p b = 1 d s p b = 0 2 . 5 3 3 . 5 4 d 0 c 0 fig. 1-1 command bit description vp0 to vp7 = f0 (h) : vp0 to vp7 = e0 (h) : vp0 to vp7 = c0 (h) playback at half (normal) speed to playback at normal (double) speed to playback at (quadruple) speed ? 43 CXD2597Q $ex commands command data 1 clv mode cm3 cm2 cm1 cm0 d3 d2 d1 d0 data 2 epwm spdc icap sfsl d3 d2 d1 d0 data 3 vc2c hifc lpwr vpon d3 d2 d1 d0 command bit cm3 cm2 cm1 description spindle stop mode. * 1 spindle forward rotation mode. * 1 spindle reverse rotation mode. valid only when lpwr = 0 in any mode. * 1 rough servo mode. when the rf-pll circuit isn't locked, this mode is used to pull the disc rotations within the rf- pll capture range. pll servo mode. automatic clvs/clvp switching mode. used for normal playback. 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva * 1 see timing charts 1-2 to 1-6. command bit epwm spdc icap description crystal reference clv servo. used for normal-speed playback in clv-w mode. * 2 spindle control with vp0 to vp7. 0 0 0 0 0 1 0 0 1 sfsl 0 0 0 vc2c 0 1 0 hifc 0 1 1 lpwr 0 0 0 vpon 0 0 1 mode clv-n clv-w cav-w * 2 figs. 3-1 and 3-2 show the control flow with the microcomputer software in clv-w mode. ? 44 CXD2597Q command data 4 spd mode gain cav1 gain cav0 0 0 d3 d2 d1 d0 gain cav1 0 0 1 1 gain cav0 0 1 0 1 gain 0db ?db ?2db ?8db this sets the gain when controlling the spindle with the phase comparator in cav-w mode. mode clv-n clv-w cav-w lpwr 0 0 1 0 1 command kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop 1-2 (a) 1-2 (b) 1-2 (c) 1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c) timing chart mode clv-n clv-w cav-w lpwr 0 0 1 0 1 0 1 1-7 1-8 1-9 1-10 (epwm = 0) 1-11 (epwm = 0) 1-12 (epwm = 1) 1-13 (epwm = 1) timing chart ? 45 CXD2597Q timing chart 1-2 clv-n mode lpwr = 0 k i c k m d p h ( a ) k i c k b r a k e m d p ( b ) b r a k e s t o p m d p ( c ) s t o p z z l z timing chart 1-3 clv-w mode (when following the spindle rotational velocity) lpwr = 0 k i c k m d p h ( a ) k i c k b r a k e m d p ( b ) b r a k e s t o p m d p ( c ) s t o p z z l z timing chart 1-4 clv-w mode (when following the spindle rotational velocity) lpwr = 1 k i c k m d p h ( a ) k i c k b r a k e m d p ( b ) b r a k e z s t o p m d p ( c ) s t o p z z timing chart 1-5 cav-w mode lpwr = 0 k i c k m d p h ( a ) k i c k b r a k e m d p ( b ) b r a k e s t o p m d p ( c ) s t o p z l timing chart 1-6 cav-w mode lpwr = 1 k i c k m d p h ( a ) k i c k b r a k e m d p ( b ) b r a k e z s t o p m d p ( c ) s t o p z ? 46 CXD2597Q timing chart 1-10 cav-w mode epwm = lpwr = 0 m d p a c c e l e r a t i o n z d e c e l e r a t i o n 2 6 4 k h z 3 . 8 s timing chart 1-7 clv-n mode lpwr = 0 m d p a c c e l e r a t i o n z d e c e l e r a t i o n 1 3 2 k h z 7 . 6 s n 2 3 6 ( n s ) n = 0 t o 3 1 timing chart 1-8 clv-w mode lpwr = 0 m d p a c c e l e r a t i o n z d e c e l e r a t i o n 2 6 4 k h z 3 . 8 s timing chart 1-9 clv-w mode lpwr = 1 m d p a c c e l e r a t i o n z 2 6 4 k h z 3 . 8 s t h e b r a k e p u l s e i s m a s k e d w h e n l p w r = 1 . timing chart 1-11 cav-w mode epwm = lpwr = 1 m d p a c c e l e r a t i o n z 2 6 4 k h z 3 . 8 s t h e b r a k e p u l s e i s m a s k e d w h e n l p w r = 1 . ? 47 CXD2597Q ?. subcode interface in the CXD2597Q, only subq can be readout. the subcodes p and r to w cannot be readout. sub q can be read out after checking crc of the 80 bits in the subcode frame. sub q can be read out from the sqso pin by inputting 80 clock pulses to the sqck pin when scor comes correctly and crcf is high. ?-1. 80-bit sub q readout fig. 2-1 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q is input, and if the crc is ok, it is output to sqso with crcf = 1. in addition, 80 bits are loaded into the parallel/serial register. when sqso goes high 400 s (monostable multivibrator time constant) or more after subcode readout, the cpu determines that the new data (which passed the crc check) has been loaded. the crcf reset is performed by inputting sqck. when the subcode data is discontinuous after track jump, etc. crcf is reset by inputting sqck. then, if crcf =1, the cpu determines that the new data has been loaded. when the 80-bit data is loaded, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered lsb first. once the 80-bit data load is confirmed, sqck is input so that the data can be read. the sqck input is detected, and the retriggerable monostable multivibrator is reset while the input is low. the retriggerable monostable multivibrator has a time constant from 270 to 400 s. when the duration when sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. while the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by crcok and others. (see timing chart 2-2.) the high and low intervals for sqck should be between 750ns and 120 s. ? 48 CXD2597Q fig. 2-1. block diagram s u b q s i n a b c d e f g h ( a f r a m ) h g f e d c b a ( a s e c ) ( a m i n ) 8 0 - b i t s / p r e g i s t e r a d d r s c t r l 8 8 8 o r d e r i n v e r s i o n 8 8 8 8 8 8 s i l d l d l d l d l d l d l d l d 8 0 - b i t p / s r e g i s t e r s o s h i f t s q c k c r c f m i x s q s o m o n o / m u l t i c r c c s u b q s h i f t ? 49 CXD2597Q timing chart 2-2 1 2 3 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 w f c k s c o r s q s o s q c k m o n o / m u l t i ( i n t e r n a l ) o r d e r i n v e r s i o n c r c f 1 d e t e r m i n e d b y m o d e l c r c f 2 8 0 c l o c k s r e g i s t e r e l o a d f o r b i d d e r 2 7 0 s t o 4 0 0 s f o r s q c k = h i g h 7 5 0 n s t o 1 2 0 s 3 0 0 n s m a x c r c f a d r 0 a d r 1 a d r 2 a d r 3 c t l 0 c t l 1 c t l 2 c t l 3 s q c k s q s o 1 2 3 ? 50 CXD2597Q timing chart 2-3 m e a s u r e m e n t i n t e r v a l ( a p p r o x i m a t e l y 3 . 8 s ) r e f e r e n c e w i n d o w ( 1 3 2 . 2 k h z ) m e a s u r e m e n t p u l s e ( v c k i / 2 ) m e a s u r e m e n t c o u n t e r v f 0 t o 7 l o a d m the relative velocity r of the disc can be expressed with the following equation. r = (r: relative velocity, m: measurement results) vf0 to vf7 is the result obtained by counting vcki/2 pulses while the reference signal (132.2khz) generated from the crystal (384fs) is high. this count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when dspb is low). m + 1 32 ? 51 CXD2597Q ?. description of modes this lsi has three basic operating modes using a combination of spindle control and the pll. the operations for each mode are described below. ?-1. clv-n mode this mode is compatible with the cxd2507aq, and operation is the same as for the conventional control. the pll capture range is 150khz. ?-2. clv-w mode this is the wide capture range mode. this mode allows the pll to follow the rotational velocity of the disc. this rotational following control has two types: using the built-in vco2 or providing an external vco. the spindle is the same clv servo as for the conventional series. operation using the built-in vco2 is described below. (when using an external vco, input the signal from the vpco pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external vco, and input the oscillation output from the vco to the vcki pin.) when starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, cav-w mode should be used. specifically, first send $e6650 to set cav-w mode and kick the disc, then send $e60c0 to set clv-w mode if alock is high, which can be readout serially from the sqso pin. clv mode can be used while alock is high. the microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (cav-w mode) when alock becomes low. the control flow according to the microcomputer software is shown in fig. 3-2. in clv-w mode (normal), low power consumption is achieved by setting lpwr to high. control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. however, when lpwr is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. note) the capture range for clv-w mode has theoretically the range up to the signal processing limit. ?-3. cav-w mode this is cav mode. in this mode, the external clock is fixed and it is possible to control the spindle to variable rotational velocity. the rotational velocity is determined by the vp0 to vp7 setting values. when controlling the spindle with vp0 to vp7, setting cav-w mode with the $e6650 command and controlling vp0 to vp7 with the $dx commands allows the rotational velocity to be varied from low speed to double speed. (see the $dx commands.) the microcomputer can know the rotational velocity using v16m. the reference for the velocity measurement is a signal of 132.3khz obtained by 1/128-frequency dividing the crystal (384fs). the velocity is obtained by counting the half of v16m pulses while the reference is high, and the result is output from the new cpu interface as 8 bits (vf0 to vf7). these measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. these values match those of the 256-n for control with vp0 to vp7. in cav-w mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. therefore, the cycles for the fs system clock, pcm data and all other output signals from this lsi change according to the rotational velocity of the disc. note) the capture range for this mode is theoretically up to the signal processing limit. ? 52 CXD2597Q c a v - w c l v s c l v - w c l v p r o t a t i o n a l v e l o c i t y t a r g e t v e l o c i t y o p e r a t i o n m o d e s p i n d l e m o d e t i m e k i c k l o c k a l o c k fig. 3-1. disc stop to normal condition in clv-w mode clv-w mode n o y e s k i c k $ e 8 0 0 0 m u t e o f f $ a 0 x x x x x a l o c k = h ? n o y e s a l o c k = l ? c l v - w m o d e s t a r t c a v - w $ e 6 6 5 0 ( c l v a ) c l v - w $ e 6 0 c 0 ( c l v a ) ( w f c k p l l ) fig. 3-2. clv-w mode flow chart ?53 CXD2597Q ?. description of other functions ?-1. channel clock recovery by digital pll circuit the channel clock is necessary for demodulating the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is modulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is the channel clock, is necessary. in an actual player, the pll is necessary to recover the channel clock because the fluctuation in the spindle rotation alters the width of the efm signal pulses. the block diagram of this pll is shown in fig. 4-1. the CXD2597Q has a built-in three-stage pll. the first-stage pll is for the wide-band pll. when the internal vco2 is used, an external lpf is necessary; when not using the internal vco2, external lpf and vco are required. the output of this first-stage pll is used as a reference for all clocks within the lsi. the second-stage pll generates the high-frequency clock needed by the third-stage digital pll. the third-stage pll is a digital pll that recovers the actual channel clock. a new digital pll has been provided for clv-w mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. ? 54 CXD2597Q block diagram 4-1 x ' t a l x t s l o s c 1 / 2 1 / 3 2 1 / n 1 / 2 m i c r o c o m p u t e r c o n t r o l n = 1 t o 2 5 6 ( v p 7 t o 0 ) 1 / k ( k s l 1 , 0 ) c l v - w c a v - w s p i n d l e r o t a t i o n i n f o r m a t i o n c l v - n c l v - w c a v - w / c l v - n p h a s e c o m p a r a t o r s e l e c t o r l p f v c o s e l 2 v c o 2 v p c o v c t l 2 / 1 m u x v p o n 1 / m 1 / n p h a s e c o m p a r a t o r v c o 1 v c o s e l 1 1 / k ( k s l 3 , 2 ) d i g i t a l p l l r f p l l p c o f i l i f i l o c l t v c x d 2 5 9 7 q ? 55 CXD2597Q ?-2. frame sync protection in normal-speed playback, a frame sync is recorded approximately every 136 s (7.35khz). this signal is used as a reference to recognize the data within a frame. conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. as a result, recognizing the frame sync properly is extremely important for improving playability. in the CXD2597Q, window protection and forward protection/backward protection have been adopted for frame sync protection. these functions achieve very powerful frame sync protection. there are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. concretely, when the disc is being played back normally and then the frame sync cannot be detected due to scratches etc., a maximum of 13 frames are inserted. if the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. in addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. ?-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed-solomon codes with a minimum distance of 5. the CXD2597Q's sec strategy uses powerful frame sync protection and c1 and c2 error correction to achieve high playability. the correction status can be monitored externally. see table 4-2. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held or an average value interpolation was made for the data. mnt3 0 0 0 1 1 1 mnt1 0 0 1 0 0 1 mnt0 0 1 1 0 1 0 description no c1 errors one c1 error corrected c1 correction impossible no c2 errors one c2 error corrected c2 correction impossible table 4-2. ? 56 CXD2597Q timing chart 4-3 n o r m a l - s p e e d p b m n t 3 m n t 1 m n t 0 t = d e p e n d e n t o n e r r o r c o n d i t i o n c 1 c o r r e c t i o n c 2 c o r r e c t i o n s t r o b e s t r o b e ?-4. da interface the CXD2597Q da interface is as described below. this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel. ? 57 CXD2597Q timing chart 4-4 l r c k ( 4 4 . 1 k ) b c k ( 2 . 1 2 m ) l r c k ( 8 8 . 2 k ) b c k ( 4 . 2 3 m ) p c m d 4 8 - b i t s l o t n o r m a l - s p e e d p l a y b a c k 1 2 4 p c m d r 0 l c h m s b ( 1 5 ) l 1 4 l 1 3 l 1 2 l 1 1 l 1 0 l 9 l 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 r m s b r 0 l c h m s b ( 1 5 ) 2 4 r c h m s b 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 8 - b i t s l o t d o u b l e - s p e e d p l a y b a c k 1 2 l 0 ? 58 CXD2597Q ?-5. digital out there are three digital out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the CXD2597Q supports type 2 form 1. sub q data which are matched twice in succession after a crc check are input to the first four bits (bits 0 to 3) of the channel status. table 4-5. ?-6. servo auto sequence this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1-track jump, 2n-track jump and n-track move are executed automatically. the commands which enable transfer to the CXD2597Q during the execution of auto sequence are $4x to $ex. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100 s after that point. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 / 1 0 0 0 i d 0 i d 1 c o p y e m p h 0 0 0 0 1 0 0 0 0 0 0 0 f r o m s u b q 0 1 6 3 2 4 8 1 7 6 b i t s 0 t o 3 s u b q c o n t r o l b i t s t h a t m a t c h e d t w i c e w i t h c r c o k b i t 2 9 1 w h e n v p o n = 1 d i g i t a l o u t c b i t 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 ? 59 CXD2597Q (a) auto focus ($47) focus search-up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to fig. 4-3. the auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). in addition, blind e of register 5 is used to eliminate fzc chattering. concretely, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. fig. 4-6-(a). auto focus flow chart a u t o f o c u s f o c u s s e a r c h u p f o k = h n o y e s f z c = h n o y e s f z c = l n o y e s e n d f o c u s s e r v o o n ( c h e c k w h e t h e r f z c i s c o n t i n u o u s l y h i g h f o r t h e p e r i o d o f t i m e e s e t w i t h r e g i s t e r 5 . ) ? 60 CXD2597Q fig. 4-6-(b). auto focus timing chart (b) track jump 1, 10 and 2n-track jumps are performed respectively. always use this when the focus, tracking, and sled servos are on. note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. 1-track jump when $48 ($49 for rev) is received from the cpu, a fwd (rev) 1-track jump is performed in accordance with fig. 4-7. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, a fwd (rev) 10-track jump is performed in accordance with fig. 4-8. the principal difference from the 1-track jump is to kick the sled. in addition, after kicking the actuator, when 5 tracks have been counted through cout, the brake is applied to the actuator. then, when the actuator speed is found to have slowed up enough (determined by the cout cycle becoming longer than the overflow c set with register 5), the tracking and sled servos are turned on. 2n-track jump when $4c ($4d for rev) is received from the cpu, a fwd (rev) 2n-track jump is performed in accordance with fig. 4-9. the track jump count n is set with register 7. although n can be set to 2 16 tracks, note that the setting is actually limited by the actuator. cout is used for counting the number of jumps. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set with register 6. n-track move when $4e ($4f for rev) is received from the cpu, a fwd (rev) n-track move is performed in accordance with fig. 4-10. n can be set to 2 16 tracks. cout is used for counting the number of jumps. the n-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. x l a t f o k ( f z c ) b u s y c o m m a n d f o r d s s p $ 4 7 l a t c h $ 0 3 b l i n d e $ 0 8 ? 61 CXD2597Q fig. 4-7-(a). 1-track jump flow chart t r a c k n o y e s e n d t r a c k f w d k i c k s l e d s e r v o o f f w a i t ( b l i n d a ) c o u t = t r a c k r e v k i c k w a i t ( b r a k e b ) t r a c k , s l e d s e r v o o n ( f w d k i c k f o r r e v j u m p ) ( r e v k i c k f o r r e v j u m p ) fig. 4-7-(b). 1-track jump timing chart x l a t c o u t b u s y c o m m a n d f o r d s s p $ 4 8 ( r e v = $ 4 9 ) l a t c h $ 2 8 ( $ 2 c ) b l i n d a b r a k e b $ 2 c ( $ 2 8 ) $ 2 5 ? 62 CXD2597Q fig. 4-8-(a). 10-track jump flow chart 1 0 t r a c k n o y e s e n d t r a c k , s l e d f w d k i c k w a i t ( b l i n d a ) c o u t = 5 ? t r a c k , r e v k i c k t r a c k s l e d s e r v o o n ( c h e c k w h e t h e r t h e c o u t c y c l e i s l o n g e r t h a n o v e r f l o w c . ) ( c o u n t s c o u t 5 ) n o y e s c = o v e r f l o w ? fig. 4-8-(b). 10-track jump timing chart x l a t c o u t b u s y c o m m a n d f o r d s s p $ 4 a ( r e v = $ 4 b ) l a t c h b l i n d a $ 2 a ( $ 2 f ) c o u t 5 c o u n t $ 2 e ( $ 2 b ) o v e r f l o w c $ 2 5 ? 63 CXD2597Q fig. 4-9-(a). 2n-track jump flow chart 2 n t r a c k n o y e s e n d t r a c k , s l e d f w d k i c k w a i t ( b l i n d a ) c o u t = n t r a c k r e v k i c k t r a c k s e r v o o n n o y e s c = o v e r f l o w w a i t ( k i c k d ) s l e d s e r v o o n fig. 4-9-(b). 2n-track jump timing chart x l a t b u s y c o m m a n d f o r d s s p b l i n d a $ 2 a ( $ 2 f ) c o u t n c o u n t $ 2 e ( $ 2 b ) o v e r f l o w c k i c k d $ 2 6 ( $ 2 7 ) $ 2 5 $ 4 c ( r e v = $ 4 d ) l a t c h c o u t ? 64 CXD2597Q fig. 4-10-(a). n-track move flow chart n t r a c k m o v e n o y e s e n d t r a c k s e r v o o f f s l e d f w d k i c k w a i t ( b l i n d a ) c o u t = n e n d t r a c k , s l e d s e r v o o f f fig. 4-10-(b). n-track move timing chart x l a t b u s y c o m m a n d f o r d s s p $ 2 2 ( $ 2 3 ) b l i n d a c o u t n c o u n t $ 2 0 $ 4 e ( r e v = $ 4 f ) l a t c h c o u t ? 65 CXD2597Q ?-7. digital clv fig. 4-11 shows the block diagram. digital clv outputs mds error and mdp error with pwm, with the sampling frequency increased up to 130hz during normal-speed playback in clvs, clvp and other modes. in addition, the digital spindle servo gain is variable. d i g i t a l c l v c l v s u / d m d s e r r o r m d p e r r o r c l v p / s m e a s u r e m e a s u r e 2 / 1 m u x o v e r s a m p l i n g f i l t e r - 1 g a i n m d s 1 / 2 m u x c l v p / s o v e r s a m p l i n g f i l t e r - 2 n o i s e s h a p e m o d u l a t i o n k i c k , b r a k e , s t o p m d p g a i n m d p fig. 4-11. block diagram clvs u/d : up/down signal from clvs servo mds error : frequency error for clvp servo mdp error : phase error for clvp servo ? 66 CXD2597Q ?-8. cd-dsp block playback speed in the CXD2597Q, the following playback modes can be selected through different combinations of the crystal, xtsl pin and the dspb command of $9x. cd-dsp block playback speed crystal 768fs 768fs 768fs 384fs 384fs 384fs 0 1 1 0 0 1 1 0 1 0 1 1 4 * 1 1 2 1 2 1 * 2 xtsl dspb cd-dsp block playback speed fs = 44.1khz. * 1 in 4 speed playback, the timer value for the auto sequence is halved. * 2 low power consumption mode. the cd-dsp processing speed is halved, allowing power consumption to be reduced. ?-9. dac block playback speed the operation speed for the dac block is determined by the crystal and the mcsl command of $9x regardless of the cd-dsp operating conditions noted above. this allows the playback modes for the dac and cd-dsp blocks to be set independently. 1-bit dac block playback speed crystal 768fs 768fs 384fs 1 0 0 1 2 1 mcsl dac block playback speed fs = 44.1khz. ? 67 CXD2597Q ?-10. description of dac block functions zero data detection when the condition where the lower 4 bits of the input data are dc and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. zero data detection is performed independently for the left and right channels. mute flag output the lmut and rmut pins go active when any one of the following conditions is met. the polarity can be selected with the zdpl command of $9x. when zero data is detected when a high signal is input to the sysm pin when the smut command of $ax is set attenuation operation assuming the attenuation commands x1, x2 and x3, the corresponding audio outputs are y1, y2 and y3 (y1 > y3 > y2). first, the command x1 is sent and then the audio approaches y1. when the command x2 is sent before the audio output reaches y1 (a in the figure), the audio output passes y1 and approaches y2. and, when the command x3 is sent before the audio output reaches y2 (b or c in the figure), the audio output approaches y3 from the value (b or c in the figure) at that point. a y 1 b y 3 c y 2 2 3 . 2 [ m s ] 0 0 0 ( h ) 0 d b 4 0 0 ( h ) ? 68 CXD2597Q dac block mute operation soft mute soft mute results and the input data is attenuated to zero when any one of the following conditions is met. when attenuation data of "000" (high) is set when the smut command of $ax is set to 1 when a high signal is input to the sysm input pin forced mute forced mute results when the fmut command of $ax is set to 1. forced mute fixes the pwm output that is input to the lpf block to low. * when setting fmut, set opsl2 to 1. (see the $ax commands.) zero detection mute forced mute is applied when the zmut command of $9x is set to 1 and the zero data is detected for the left and right channels. (see "zero data detection".) when the zmut command of $9x is set to 1, the forced mute is applied even if the mute flag output condition is met. when the zero detection mute is on, set the dcof command of $9x to 1. s o f t m u t e o n s o f t m u t e o f f s o f t m u t e o f f 2 3 . 2 [ m s ] 2 3 . 2 [ m s ] 0 d b d b ? 69 CXD2597Q n o r m a l d b b m i d d b b m a x 1 0 . 0 0 4 . 0 0 6 . 0 0 4 . 0 0 2 . 0 0 0 . 0 0 2 . 0 0 8 . 0 0 6 . 0 0 8 . 0 0 1 0 . 0 0 1 2 . 0 0 1 4 . 0 0 1 0 3 0 1 0 0 3 0 0 1 k 3 k 1 0 k 3 0 k d i g i t a l b a s s b o o s t f r e q u e n c y r e s p o n s e [ h z ] [ d b ] graph 4-12. lrck synchronization synchronization is performed at the first falling edge of the lrck input during reset. after that, synchronization is lost when the lrck input frequency changes and resynchronization must be performed. the lrck input frequency changes when the master clock of the lsi is switched and the playback speed changes such as the following cases. when the xtsl pin switches between high and low when the dspb command of $9x setting changes when the mcsl command of $9x setting changes for resynchronization, set the lrwo command of $ax to 1, wait for one lrck cycle or more, and then set lrwo to 0. * when setting lrwo, set opsl2 to 1. (see the $ax commands.) digital bass boost bass boost without external parts is possible using the built-in digital filter. the boost strength has two levels: mid. and max. bsbst and bbsl of address a are used for the setting. see graph 4-12 for the digital bass boost frequency response. ? 70 CXD2597Q a n a l o g o u t c 2 6 8 0 p 1 2 k 1 2 k 1 2 k c 1 1 5 0 p a o u t 1 ( 2 ) a i n 1 ( 2 ) l o u t 1 ( 2 ) v c fig. 4-13. lpf external circuit ?-11. lpf block the CXD2597Q contains an initial-stage secondary active lpf with numerous resistors and capacitors and an operational amplifier with reference voltage. the resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. the reference voltage (v c ) is (av dd ?av ss ) 0.43. the lpf block application circuit is shown below. in this circuit, the cut-off frequency is fc 40khz. the external capacitors' values when fc = 30khz and 50khz are noted below as a reference. the resistors' values do not change at this time. ? when fc 30khz: c1 = 200pf, c2 = 910pf when fc 50khz: c1 = 120pf, c2 = 560pf lpf block application circuit ? 71 CXD2597Q ?-12. asymmetry correction fig. 4-14 shows the block diagram and circuit example. r f a c r 1 r 1 a s y o a s y i r 1 2 r 2 5 = b i a s r 1 r 1 r 2 c x d 2 5 9 7 q fig. 4-14. asymmetry correction application circuit ? 72 CXD2597Q ?-13. cd text data demodulation in order to demodulate the cd text data, set the command $8 data 6 d3 txon to 1. during txon = 1 it requires 26.7ms (max.) to demodulate the cd text data correctly after txon is set to 1. the cd text data is output by switching the sqso pin with the command. the cd text data output is enabled by setting the command $8 data 6 d2 txout to 1. to read data, the readout clock should be input to sqck. the readable data are the crc counting results for the each pack and the cd text data (16 bytes) except for crc data. when the cd text data is read, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered lsb first. data which can be stored in the lsi is 1 packet (4 packs). fig. 4-15. block diagram of cd text demodulation circuit s q c k s q s o t x o u t s u b c o d e d e c o d e r c d t e x t d e c o d e r ? 73 CXD2597Q c r c 4 c r c 3 c r c 2 c r c 1 0 0 0 0 s 2 r 2 w 1 v 1 u 1 t 1 s 1 r 1 u 3 t 3 s 3 r 3 w 2 v 2 u 2 t 2 w 4 v 4 u 4 t 4 s 4 c r c d a t a i d 1 ( p a c k 1 ) i d 2 ( p a c k 1 ) i d 3 ( p a c k 1 ) 1 6 b y t e 1 6 b y t e 1 6 b y t e 1 6 b y t e 4 b i t 4 b i t s u b c o d e q d a t a s c o r t x o u t ( c o m m a n d ) s q c k s q s o s q c k t x o u t ( c o m m a n d ) l s b m s b l s b m s b l s b c r c 0 p a c k 1 p a c k 2 p a c k 3 p a c k 4 c r c f c r c f 8 0 c l o c k s q s o 5 2 0 c l o c k fig. 4-16. cd text data timing chart ? 74 CXD2597Q ?. description of servo signal processing system functions and commands ?-1. general description of servo signal processing system (v dd : supply voltage) focus servo sampling rate: 88.2khz (when mck = 128fs) input range: 0.3v dd to 0.7v dd output format: 7-bit pwm others: offset cancel focus bias adjustment focus search gain-down function defect countermeasure auto gain control tracking servo sampling rate: 88.2khz (when mck = 128fs) input range: 0.3v dd to 0.7v dd output format: 7-bit pwm others: offset cancel e:f balance adjustment track jump gain-up function defect countermeasure drive cancel auto gain control vibration countermeasure sled servo sampling rate: 345hz (when mck = 128fs) input range: 0.3v dd to 0.7v dd output format: 7-bit pwm others: sled move fok, mirr, dfct signals generation rf signal sampling rate: 1.4mhz (when mck = 128fs) input range: 0.43v dd to v dd others: rf zero level automatic measurement ? 75 CXD2597Q ?-2. digital servo block master clock (mck) the clock with the 2/3 frequency of the crystal is supplied to the digital servo block. the xt4d and xt2d commands can be set with d13 and d12 of $3f, and the xt1d command can be set with d1 of $3e. (default = 0) the digital servo block is designed with an mck frequency of 5.6448mhz (128fs) as typical. mode 1 2 3 4 5 6 7 384fs 384fs 384fs 768fs 768fs 768fs 768fs 256fs 256fs 256fs 512fs 512fs 512fs 512fs * * 0 * * * 1 * * 0 * * 1 0 * 1 0 * 1 0 0 1 0 0 1 0 0 0 1 1/2 1/2 1 1/2 1/4 1/4 256fs 128fs 128fs 512fs 256fs 128fs 128fs xtli input to servo xtsl xt4d xt2d xt1d frequency division ratio mck fs = 44.1khz, * : don? care table 5-1. ?-3. avrg (average) measurement and compensation the CXD2597Q has a circuit that measures the averages of rfdc, vc, fe and te and a circuit that compensates these signals to control the servo effectively. avrg measurement and compensation is necessary to initialize the CXD2597Q, and is able to cancel the offset. the level applied to the vc, fe, rfdc and te pins can be measured by setting d15 (vclm), d13 (flm), d11 (rflm) and d4 (tclm) of $38 respectively to 1. avrg measurement takes the level applied to each analog input pin as the average of 256 samples, and then loads each value into the avrg register. avrg measurement requires approximately 2.9ms to 5.8ms (when mck = 128fs) after the command is received. during avrg measurement, if the upper 8 bits of the command register are 38 (hex), the completion of avrg measurement operation can be confirmed through the sens pin. (see timing chart 5-2.) x l a t s e n s ( = x a v e b s y ) m a x . 1 s c o m p l e t i o n o f a v r g m e a s u r e m e n t 2 . 9 t o 5 . 8 m s timing chart 5-2. ? 76 CXD2597Q ? 77 CXD2597Q ?-4. e:f balance adjustment function when the disc is rotated with the laser on, and with the fcs (focus) servo on via fcs search (focus search), the traverse waveform appears in the te signal due to disc eccentricity. in this condition, the low-frequency component can be extracted from the te signal using the built-in trk hold filter by setting d5 (tblm) of $38 to 1. the extracted low-frequency component is loaded into the trvsc register as a digital value, and the trvsc register value is established when tblm returns to 0. next, setting d2 (tlc2) of $38 to 1 compensates te and se values with the trvsc register value (subtraction), making the e:f balance offset to be adjusted as a result. (see fig. 5-3.) ?-5. fcs bias (focus bias) adjustment function the fbias register value can be added to the fcs servo filter input by setting d14 (fbon) of $3a to 1. (see fig. 5-3.) when the fbias register value is set when d11 = 0 and d10 = 1 with $34f, data can be written using the 9-bit value of d9 to d1 (d9: msb). in addition, the rf jitter can be monitored by setting the soct command of $8 to 1. (see "dsp block timing chart".) the fbias register can be used as a counter by setting d13 (fbss) of $3a to 1. the fbias register functions as an up counter when d12 (fbup) of $3a = 1, and as a down counter when d12 (fbup) of $3a = 0. the number of up and down steps can be changed by setting d11 and d10 (fbv1 and fbv0) of $3a. when using the fbias register as a counter, the counter stops if the fcsbias value and the value set beforehand in fbl9 to fbl1 of $34 matches. also, if the upper 8 bits of the command register are $3a at this time, sens becomes high and the counter stop can be monitored. a b c f b i a s s e t t i n g v a l u e ( f b 9 t o f b 1 ) l i m i t v a l u e ( f b l 9 t o f b l 1 ) s e n s v a l u e a : r e g i s t e r m o d e b : c o u n t e r m o d e c : c o u n t e r m o d e ( w h e n s t o p p e d ) here, assume the fbias setting value fb9 to fb1 and the fbias limit value fbl9 to fbl1 like status a. for example, if command registers fbup = 0, fbv1 = 0, fbv0 = 0 and fbss = 1 are set from this status, down count starts from status a and approaches the set limit value. when the fcsbias value matches fbl9 to fbl1, the counter stops and the sens pin goes to high. note that the up/down counter counts at each sampling cycle of the focus servo filter. the number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by fbv1 and fbv0. when converted to fe input, 1 step corresponds to 1/512 v dd 0.4. ? 78 CXD2597Q t e a v r g r e g i s t e r t l c 1 t r v s c r e g i s t e r t l c 2 t o t r k i n r e g i s t e r v c a v r g r e g i s t e r t l c 0 v c l c t e f r o m a / d f e a v r g r e g i s t e r f l c 1 f b i a s r e g i s t e r f b o n t o f c s i n r e g i s t e r f l c 0 t o f z c r e g i s t e r f e f r o m a / d r f l c t o r f i n r e g i s t e r r f d c f r o m a / d r f a v r g r e g i s t e r t o s l d i n r e g i s t e r s e f r o m a / d t l c 0 t l d 0 t l c 1 t l d 1 t l c 2 t l d 2 fig. 5-3. ? 79 CXD2597Q ?-6. agcntl (automatic gain control) function the agcntl function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. agcntl not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. the agcntl command is sent when each servo is turned on. during agcntl operation, if the upper 8 bits of the command register are 38 (hex), the completion of agcntl operation can be confirmed through the sens pin. (see timing chart 5-4 and "description of sens signals".) setting d9 and d8 of $38 to 1 set fcs (focus) and trk (tracking) respectively to agcntl operation. note) during agcntl operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. x l a t s e n s ( = a g o k ) m a x . 1 1 . 4 s a g c n t l c o m p l e t i o n timing chart 5-4. coefficient k13 changes for agf (focus agcntl) and coefficients k23 and k07 change for agt (tracking agcntl) due to agcntl. these coefficients change from 01 to 7f (hex), and they must also be set within this range when written externally. after agcntl operation has completed, these coefficient values can be confirmed by reading them out from the sens pin with the serial readout function (described hereafter). agcntl related settings the following settings can be changed with $35, $36 and $37. fg6 to fg0; agf convergence gain setting, effective setting range: 00 to 57 (hex) tg6 to tg0; agt convergence gain setting, effective setting range: 00 to 57 (hex) ags; self-stop on/off agj; convergence completion judgment time aggf; internally generated sine wave amplitude (agf) aggt; internally generated sine wave amplitude (agt) agv1; agcntl sensitivity 1 (during rough adjustment) agv2; agcntl sensitivity 2 (during fine adjustment) aghs; rough adjustment on/off aght; fine adjustment time note) converging servo loop gain values can be changed with the fg6 to fg0 and tg6 to tg0 setting values. in addition, these setting values must be within the effective setting range. the default settings aim for 0 db at 1khz. however, since convergence values vary according to the characteristics of each constituent element of the servo loop, fg and tg values should be set as necessary. ? 80 CXD2597Q agcntl and default operation have two stages. in the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with aght, when mck = 128fs), and the agcntl coefficient approaches the appropriate value. the sensitivity at this time can be selected from two types with agv1. in the second stage, the agcntl coefficient is finely adjusted to approach more appropriate value with relatively low sensitivity. the sensitivity for the second stage can be selected from two types with agv2. in the second stage of default operation, when the agcntl coefficient reaches the appropriate value and stops changing, the CXD2597Q confirms that the agcntl coefficient has not changed for a certain period of time (select 63/31ms with aghj, when mck = 128fs), and then completes agcntl operation. (self-stop mode) this self-stop mode can be canceled by setting ags to 0. in addition, the first stage is omitted for agcntl operation when aghs is set to 0. an example of agcntl coefficient transitions during agcntl in various settings are shown in fig. 5-5. i n i t i a l v a l u e s e n s a g c n t l s t a r t a g c n t l c o m p l e t i o n c o n v e r g e n c e v a l u e a g c n t l c o e f f i c i e n t v a l u e s l o p e a g v 1 a g h t a g j s l o p e a g v 2 fig. 5-5. note) fig. 5-5 shows the example where the agcntl coefficient value converges to the smaller value from the initial value. ? 81 CXD2597Q ?-7. fcs servo and fcs search (focus search) the fcs servo is controlled by the 8-bit serial command $0x. (see table 5-6.) register name command d23 to d20 d19 to d16 1 0 * * 1 1 * * 0 * 0 * 0 * 1 * 0 * 1 0 0 * 1 1 focus se r vo on (focus gain normal) focus se r vo on (focus gain down) focus se r vo off, 0v out focus se r vo off, focus search voltage out focus search voltage down focus search voltage up 0 0 0 0 focus control 0 table 5-6. fcs search fcs search is required in the course of turning on the fcs servo. fig. 5-7 shows the signals for sending commands $00 ? $02 ? $03 and performing only fcs search operation. fig. 5-8 shows the signals for sending $08 (fcs on) after that. f c s d r v r f f o k f e f z c f z c c o m p a r a t o r l e v e l $ 0 0 $ 0 2 $ 0 3 0 0 f c s d r v r f f o k f e f z c $ 0 0 $ 0 2 $ 0 3 0 $ 0 8 fig. 5-7. fig. 5-8. * : don? care ? 82 CXD2597Q ?-8. trk (tracking) and sld (sled) servo control the trk and sld servos are controlled by the 8-bit command $2x. (see table 5-9.) when the upper 4 bits of the serial data are 2 (hex), tzc is output to the sens pin. d23 to d20 d19 to d16 0 0 * * 0 1 * * 1 0 * * 1 1 * * * * 0 0 * * 0 1 * * 1 0 * * 1 1 tracking se r vo off tracking se r vo on forward track jump reverse track jump sled se r vo off sled se r vo on forward sled move reverse sled move 0 0 1 0 tracking mode 2 table 5-9. trk servo the trk jump (track jump) level can be set with 6 bits (d13 to d8) of $36. in addition, when the trk servo is on and d17 of $1 is set to 1, the trk servo filter switches to gain-up mode. the filter also switches to gain-up mode when the lock signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. the CXD2597Q has two types of filters in trk gain-up mode which can be selected by setting d16 of $1. (see table 5-17.) sld servo the sld mov (sled move) output, composed of a basic value from 6 bits (d13 to d8) of $37, is determined by multiplying this value by 1 , 2 , 3 or 4 magnification set using d17 and d16 when d18 = d19 = 0 is set with $3. (see table 5-10.) sld mov must be performed continuously for 50 s or more. in addition, if the lock input signal goes low when the sld servo is on, the sld servo turns off. note) when the lock signal is low, the trk servo switches to gain-up mode and the sld servo is turned off by the default. these operations are disabled by setting d6 (lksw) of $38 to 1. d23 to d20 d19 to d16 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 sled kick level (basic value 1) sled kick level (basic value 2) sled kick level (basic value 3) sled kick level (basic value 4) 0 0 1 1 select 3 table 5-10. * : don? care register name command register name command ? 83 CXD2597Q ?-9. mirr and dfct signal generation the rf signal obtained from the rfdc pin is sampled at approximately 1.4mhz (when mck = 128fs) and loaded. the mirr and dfct signals are generated from this rf signal. mirr signal generation the loaded rf signal is applied to the peak hold and bottom hold circuits. an envelope is generated from the waveforms generated in these circuits, and the mirr comparator level is generated from the average of this envelope waveform. the mirr signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this mirr comparator level. (see fig. 5-11.) the bottom hold speed and mirror sensitivity can be selected from 4 values using d7 and d6, and d5 and d4, respectively, of $3c. r f p e a k h o l d b o t t o m h o l d p e a k h o l d b o t t o m h o l d m i r r m i r r c o m p ( m i r r o r c o m p a r a t o r l e v e l ) h l r f p e a k h o l d 1 p e a k h o l d 2 p e a k h o l d 2 p e a k h o l d 1 d f c t ( d e f e c t c o m p a r a t o r l e v e l ) h l s d f fig. 5-11. dfct signal generation the loaded rf signal is input to two peak hold circuits with different time constants, and the dfct signal is generated by comparing the difference between these two peak hold waveforms with the dfct comparator level. (see fig. 5-12.) the dfct comparator level can be selected from four values using d13 and d12 of $3b. fig. 5-12. ? 84 CXD2597Q ?-10. dfct countermeasure circuit the dfct countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. specifically, these operations are achieved by detecting scratch and defect with the dfct signal generation circuit, and when dfct goes high, applying the low-frequency component of the error signal before dfct went high to the fcs and trk servo filter inputs. (see fig. 5-13.) in addition, these operations are activated by the default. they can be disabled by setting d7 (dfsw) of $38 to 1. i n p u t r e g i s t e r h o l d r e g i s t e r h o l d f i l t e r s e r v o f i l t e r e n e r r o r s i g n a l d f c t fig. 5-13. ?-11. anti-shock circuit when vibrations occurs in the cd player, this circuit forces the trk filter to switch to gain-up mode so that the servo does not become easily dislocated. this circuit is for systems which require vibration countermeasures. concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (see fig. 5-14.) the comparator level is fixed to 1/16 of the maximum comparator input amplitude. however, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient k35. this function can be turned on and off by d19 of $1 when the brake circuit (described hereafter) is off. (see table 5-17.) this circuit can also support an external vibration detection circuit, and can set the trk servo filter to gain-up mode by inputting high level to the atsk pin. when the upper 4 bits of the command register are 1 (hex), vibration detection can be monitored from the sens pin. it also can be monitored from the atsk pin by setting the asot command of $3f. t e a n t i s h o c k f i l t e r t r k g a i n u p f i l t e r t r k g a i n n o r m a l f i l t e r t r k p w m g e n a t s k s e n s c o m p a r a t o r fig. 5-14. ? 85 CXD2597Q ?-12. brake circuit immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. the brake circuit prevents these phenomenon. the brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180 offset in the rf envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (see figs. 5-15 and 5-16.) concretely, this operation is achieved by masking the tracking drive using the trkcncl signal generated by loading the mirr signal at the edge of the tzc (tracking zero cross) signal. the brake circuit can be turned on and off by d18 of $1. (see fig. 5-17.) t r k d r v f w d j m p r e v j m p s e r v o o n r f t r a c e m i r r t e 0 0 t z c e d g e t r k c n c l t r k d r v s e n s t z c o u t i n n e r t r a c k o u t e r t r a c k t r k d r v r e v j m p f w d j m p s e r v o o n r f t r a c e m i r r t e 0 0 t z c e d g e t r k c n c l t r k d r v s e n s t z c o u t o u t e r t r a c k i n n e r t r a c k fig. 5-15. fig. 5-16. d23 to d20 d19 to d16 1 0 * * 0 * * * * 1 * * * 0 * * * * 0 * * * 1 * * * * 1 * * * 0 anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 0 0 0 1 tracking control 1 fig. 5-17. * : don? care register name command ? 86 CXD2597Q ?-13. cout signal the cout signal is output to count the number of tracks during traverse, etc. it is basically generated by loading the mirr signal at both edges of the tzc signal. and the used tzc signal can be selected among three different phases for each cout signal application. hptzc: for 1-track jumps fast phase cout signal generation with a fast phase tzc signal. (the tzc phase is advanced by a cut-off 1khz digital hpf; when mck = 128fs.) stzc: for cout signal generation when mirr is externally input and for applications other than cout generation. this is generated from sampling te at 700khz. (when mck = 128fs) dtzc: for high-speed traverse reliable cout signal generation with a delayed phase stzc signal. since it takes some time to generate the mirr signal, it is necessary to delay the tzc signal in accordance with the mirr signal delay during high-speed traverse. the cout signal output method is switched with d15 and d14 of $3c. when d15 = 1 : stzc when d15 = 0 and d14 = 0 : hptzc when d15 = 0 and d14 = 1 : dtzc when the dtzc is selected, the delay can be selected from two values with d14 of $36. ?-14. serial readout circuit the following measurement and adjustment results can be readout from the sens pin by inputting the readout clock to the sclk pin by $39. (see fig. 5-18, table 5-19 and "description of sens signals".) specified commands $390c: vc avrg measurement result $3908: fe avrg measurement result $3904: te avrg measurement result $391f: rf avrg measurement result $3953: fcs agcntl coefficient result $3963: trk agcntl coefficient result $391c: trvsc adjustment result $391d: fbias register value t d l s t s p w 1 / f s c l k m s b l s b x l a t s c l k s e r i a l r e a d o u t d a t a ( s e n s ) item symbol min. typ. max. unit sclk frequency sclk pulse width delay time f sclk t spw t dls 31.3 15 16 mhz ns s table 5-19. during readout, the upper 8 bits of the command register must be 39 (hex). fig. 5-18. ? 87 CXD2597Q ?-15. writing to coefficient ram the coefficient ram can be rewritten by $34. all coefficients have default values in the built-in rom, and transfer from the rom to the ram is completed approximately 40 s (when mck = 128fs) after the xrst pin rises. (the coefficient ram cannot be rewritten during this period.) after that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient ram. the coefficient rewrite command is comprised of 24 bits, with d14 to d8 of $34 as the address (d15 = 0) and d7 to d0 as data. coefficient rewriting is completed 11.3 s (when mck = 128fs) after the command is received. when rewriting multiple coefficients continuously, be sure to wait 11.3 s (when mck = 128fs) before sending the next rewrite command. ?-16. pwm output fcs, trk and sld outputs are output as pwm waveforms. in particular, fcs and trk permit accurate drive by using a double oversampling noise shaper. timing chart 5-20 and fig. 5-21 show examples of output waveforms and drive circuits. t mck = 180ns timing chart 5-20. 6 4 t m c k 6 4 t m c k 6 4 t m c k a t m c k a t m c k s f d r s r d r s l d 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k f c s / t r k f f d r / t f d r f r d r / t r d r o u t p u t v a l u e + a o u t p u t v a l u e a o u t p u t v a l u e 0 t m c k a 2 t m c k a 2 t m c k a 2 t m c k a 2 m c k ( 5 . 6 4 4 8 m h z ) - - - - - - - 1 5.6448mhz ? 88 CXD2597Q example of driver circuit r d r f d r 2 2 k 2 2 k 2 2 k 2 2 k d r v v c c v e e fig. 5-21. driver circuit ? 89 CXD2597Q ?-17. servo status changes produced by lock signal when the lock signal becomes low, the trk servo switches to the gain-up mode and the sld servo turns off in order to prevent sld free-running. setting d6 (lksw) of $38 to 1 deactivates this function. in other words, neither the trk servo nor the sld servo change even when the lock signal becomes low. this enables microcomputer control. ?-18. description of commands and data sets the following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. input conversion converts these voltages into the voltages entering input pins before a/d conversion. output conversion converts pwm output values into analog voltage values. ? 90 CXD2597Q d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 ka6 ka5 ka4 ka3 ka2 ka1 ka0 kd7 kd6 kd5 kd4 kd3 kd2 kd1 kd0 when d15 = 0 ka6 to ka0: coefficient address kd7 to kd0: coefficient data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 1 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 when d15 = d14 = d13 = d12 = 1 ($34f) d11 = 0, d10 = 1 fbias register write fb9 to fb1: data; fb9 is msb two's complement data. for fe input conversion, fb9 to fb1 = 011111111 corresponds to 255/256 v dd /5 and fb9 to fb1 = 100000000 to ?56/256 v dd /5 respectively. (v dd : supply voltage) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 0 fbl9 fbl8 fbl7 fbl6 fbl5 fbl4 fbl3 fbl2 fbl1 when d15 = d14 = d13 = d12 = d11 = 1 ($34f) d10 = 0 fbias limit register write fbl9 to fbl1: data; data compared with fb9 to fb1, fbl9 = msb. when using the fbias register in counter mode, counter operation stops when the value of fb9 to fb1 matches with fbl9 to 1. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 0 tv9 tv8 tv7 tv6 tv5 tv4 tv3 tv2 tv1 tv0 when d15 = d14 = d13 = d12 = 1 ($34f) d11 = 0, d10 = 0 trvsc register write tv9 to tv0: data; tv9 is msb two's complement data. for te input conversion, tv9 to tv0 = 0011111111 corresponds to 255/256 v dd /5 and tv9 to tv0 = 1100000000 to ?56/256 v dd /5 respectively. (v dd : supply voltage) note) when the trvsc register is readout, the data length is 9 bits. at this time, data corresponding to each bit tv8 to tv0 during external write are readout. when reading out internally measured values and then writing these values externally, set tv9 the same as tv8. $34 ? 91 CXD2597Q $35 (preset: $35 58 2d) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ft1 ft0 fs5 fs4 fs3 fs2 fs1 fs0 ftz fg6 fg5 fg4 fg3 fg2 fg1 fg0 ft1, ft0, ftz: focus search-up speed default value: 010 (0.673 v dd v/s) focus drive output conversion ft1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1.35 v dd 0.673 v dd 0.449 v dd 0.336 v dd 1.79 v dd 1.08 v dd 0.897 v dd 0.769 v dd ft0 ftz focus search speed [v/s] fs5 to fs0: focus search limit voltage default value: 011000 ( 24/64 v dd , v dd : pwm driver supply voltage) focus drive output conversion fg6 to fg0: agf convergence gain setting value default value: 0101101 $36 (preset: $36 0e 2e) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tdzc dtzc tj5 tj4 tj3 tj2 tj1 tj0 sfjp tg6 tg5 tg4 tg3 tg2 tg1 tg0 tdzc: selects the tzc signal for generating the trkcncl signal during brake circuit operation. tdzc = 0: the edge of the hptzc or stzc signal, whichever has the faster phase, is used. tdzc = 1: the edge of the hptzc or stzc signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (see ?-12.) dtzc: dtzc delay (8.5/4.25 s, when mck = 128fs) default value: 0 (4.25 s) tj5 to tj0: track jump voltage default value: 001110 ( 14/64 v dd , v dd : pwm driver supply voltage) tracking drive output conversion sfjp: surf jump mode on/off the tracking pwm output is made by adding the tracking filter output and tjreg (tj5 to tj0), by setting d7 to 1 (on) tg6 to tg0: agt convergence gain setting value default value: 0101110 * * : preset, v dd : pwm driver supply voltage ? 92 CXD2597Q $37 (preset: $37 50 ba) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fzsh fzsl sm5 sm4 sm3 sm2 sm1 sm0 ags agj aggf aggt agv1 agv2 aghs aght fzsh, fzsl: fzc (focus zero cross) slice level default value: 01 (1/8 v dd 0.4, v dd : supply voltage); fe input conversion fzsh 0 0 1 1 0 1 0 1 1/4 v dd 0.4 1/8 v dd 0.4 1/16 v dd 0.4 1/32 v dd 0.4 fzsl slice level sm5 to sm0: sled move voltage default value: 010000 ( 16/64 v dd , v dd : pwm driver supply voltage) sled drive output conversion ags: agcntl self-stop on/off default value: 1 (on) agj: agcntl convergence completion judgment time during low sensitivity adjustment (31/63ms, when mck = 128fs) default value: 0 (63ms) aggf: focus agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggt: tracking agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggf 0 (small) 1 (large) * 1/32 v dd 0.4 1/16 v dd 0.4 1/16 v dd 0.4 1/8 v dd 0.4 aggt 0 (small) 1 (large) * fe/te input conversion agv1: agcntl convergence sensitivity during high sensitivity adjustment; high/low default value: 1 (high) agv2: agcntl convergence sensitivity during low sensitivity adjustment; high/low default value: 0 (low) aghs: agcntl high sensitivity adjustment on/off default value: 1 (on) aght: agcntl high sensitivity adjustment time (128/256ms, when mck = 128fs) default value: 0 (256ms) * * : preset * : preset ? 93 CXD2597Q $38 (preset: $38 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vclm vclc flm flc0 rflm rflc agf agt dfsw lksw tblm tclm flc1 tlc2 tlc1 tlc0 vclm: vc level measurement (on/off) vclc: vc level compensation for fcs in register (on/off) flm: focus zero level measurement (on/off) flc0: focus zero level compensation for fzc register (on/off) rflm: rf zero level measurement (on/off) rflc: rf zero level compensation (on/off) agf: focus auto gain adjustment (on/off) agt: tracking auto gain adjustment (on/off) dfsw: defect disable switch (on/off) setting this switch to 1 (on) disables the defect countermeasure circuit. lksw: lock switch (on/off) setting this switch to 1 (on) disables the sled free-running prevention circuit. tblm: traverse center measurement (on/off) tclm: tracking zero level measurement (on/off) flc1: focus zero level compensation for fcs in register (on/off) tlc2: traverse center compensation (on/off) tlc1: tracking zero level compensation (on/off) tlc0: vc level compensation for trk/sld in register (on/off) note) commands marked with are accepted every 2.9ms. (when mck = 128fs) all commands are on when set to 1. ? 94 CXD2597Q sd6 1 0 0 1 0 data ram data for address = sd4 to sd0 coefficient ram data for address = sd5 to sd0 sd4 1 0 sd3 to sd0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 * * 1 0 * * 0 1 * * 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 rf avrg register rfdc input signal fbias register trvsc register rfdc envelope (bottom) rfdc envelope (peak) rfdc envelope (peak) ?(bottom) vc avrg register fe avrg register te avrg register fe input signal te input signal se input signal vc input signal 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits $399f $399e $399d $399c $3993 $3992 $3991 $398c $3988 $3984 $3983 $3982 $3981 $3980 8 bits 16 bits sd5 readout data readout data length note) coefficients k40 to k4f cannot be readout. * : don't care see the description for sro1 of $3f concerning readout methods for the above data. d15 d14 d13 d12 d11 d10 d9 d8 dac sd6 sd5 sd4 sd3 sd2 sd1 sd0 dac: serial data readout dac mode (on/off) sd6 to sd0: serial readout data select $39 ? 95 CXD2597Q $3a (preset: $3a 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 fbon fbss fbup fbv1 fbv0 0 tjd0 fps1 fps0 tps1 tps0 0 sjhd inbk mti0 fbon: fbias (focus bias) register addition (on/off) the fbias register value is added to the signal loaded into the fcs in register by fbon = 1 (on). fbss: fbias (focus bias) register/counter switching fbss = 0: register, fbss = 1: counter. fbup: fbias (focus bias) counter up/down operation switching this performs counter up/down control when fbss = 1. fbup = 0: down counter, fbup = 1: up counter. fbv1, fbv0: fbias (focus bias) counter voltage switching the number of fcs bias count-up/-down steps per cycle is decided by these bits. tjd0: this sets the tracking servo filter data ram to 0 when switched from track jump to servo on only when sfjp = 1 (during surf jump operation). fps1, fps0: gain setting when transferring data from the focus filter to the pwm block. tps1, tps0: gain setting when transferring data from the tracking filter to the pwm block. this is effective for increasing the overall gain in order to widen the servo band. operation when fps1, fps0 (tps1, tps0) = 00 is the same as usual (7-bit shift). however, 6db, 12db and 18db can be selected independently for focus and tracking by setting the relative gain to 0db when fps1, fps0 (tps1, tps0) = 00. sjhd: this holds the tracking filter output at the value when surf jump starts during surf jump. inbk: when inbk = 0 (off), the brake circuit masks the tracking drive signal with trkcncl which is generated by taking the mirr signal at the tzc edge. when inbk = 1 (on), the tracking filter input is masked instead of the drive output. mti0: the tracking filter input is masked when the mirr signal is high by setting mti0 = 1 (on). the counter changes once for each sampling cycle of the focus servo filter. when mck is 128fs, the sampling frequency is 88.2khz. when converted to fe input, 1 step is approximately 1/2 9 v dd 0.4, v dd = supply voltage. fbv1 0 0 1 1 0 1 0 1 1 2 4 8 fbv0 number of steps per cycle fps1 0 0 1 1 fps0 0 1 0 1 0db +6db +12db +18db relative gain tps1 0 0 1 1 tps0 0 1 0 1 0db +6db +12db +18db relative gain * * : preset * * : preset * ? 96 CXD2597Q $3b (preset: $3b e0 50) sfox, sfo2, sfo1: fok slice level default value: 011 (28/256 v dd 0.57, v dd = supply voltage) rfdc input conversion sfox 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 16/256 v dd 0.57 20/256 v dd 0.57 24/256 v dd 0.57 28/256 v dd 0.57 32/256 v dd 0.57 40/256 v dd 0.57 48/256 v dd 0.57 50/256 v dd 0.57 sfo2 0 1 0 1 0 1 0 1 sfo1 slice level d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sfo2 sfo1 sdf2 sdf1 max2 max1 sfox btf d2v2 d2v1 d1v2 d1v1 rint 0 0 0 * : preset * ? 97 CXD2597Q sdf2, sdf1: dfct slice level default value: 10 (0.0313 v dd 1.14v) rfdc input conversion sdf2 0 0 1 1 0 1 0 1 0.0156 v dd 1.14 0.0234 v dd 1.14 0.0313 v dd 1.14 0.0391 v dd 1.14 sdf1 slice level max2, max1: dfct maximum time (mck = 128fs) default value: 00 (no timer limit) max2 0 0 1 1 0 1 0 1 no timer limit 2.00ms 2.36 2.72 max1 dfct maximum time btf: bottom hold double-speed count-up mode for mirr signal generation on/off (default: off) on when set to 1. d2v2, d2v1: peak hold 2 for dfct signal generation count-down speed setting default value: 01 (0.086 v dd 1.14v/ms, 44.1khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. d1v2, d1v1: peak hold 1 for dfct signal generation count-down speed setting default value: 01 (0.688 v dd 1.14v/ms, 352.8khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. rint: this initializes the initial-state registers of the circuits which generate mirr, dfct and fok. d2v2 0 0 1 1 0 1 0 1 22.05 44.1 88.2 176.4 0.0431 v dd 1.14 0.0861 v dd 1.14 0.172 v dd 1.14 0.344 v dd 1.14 d2v1 count-down speed [v/ms] [khz] * : preset, v dd : supply voltage * d2v2 0 0 1 1 0 1 0 1 176.4 352.8 705.6 1411.2 0.344 v dd 1.14 0.688 v dd 1.14 1.38 v dd 1.14 2.75 v dd 1.14 d2v1 count-down speed [v/ms] [khz] * : preset, v dd : supply voltage * * : preset, v dd : supply voltage * * : preset * ? 98 CXD2597Q $3c (preset: $3c 00 80) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 coss cots 0 0 cot2 cot1 mot2 0 bts1 bts0 mrc1 mrc0 0 0 0 0 coss, cots: these select the tzc signal used when generating the cout signal. preset = hptzc. stzc is the tzc generated by sampling the te signal at 700khz. (when mck = 128fs) dtzc is the delayed phase stzc. (the delay amount can be selected by d14 of $36.) hptzc is the fast phase tzc passed through a hpf with a cut-off frequency of 1khz. see ?-13. these commands output the tzc signal. cot2, cot1: this outputs the tzc signal from the cout pin. coss 1 0 0 0 1 stzc hptzc dtzc cots tzc * : preset, ? don't care * bts1 0 0 1 1 0 1 0 1 1 2 4 8 bts0 number of count-up steps per cycle mrc1 0 0 1 1 0 1 0 1 5.669 * 11.338 22.675 45.351 mrc0 setting time [ s] * : preset (when mck = 128fs) * mot2: the stzc signal is output from the mirr pin by setting mot2 to 1. these commands set the mirr signal generation circuit. bts1, bts0: this sets the count-up speed for the bottom hold value of the mirr generation circuit. the time per step is approximately 708 ns (when mck = 128fs). the preset value is bts1 = 1, bts0 = 0. however, this is valid only when btf of $3b is 0. mrc1, mrc0: this sets the minimum pulse width for masking the mirr signal of the mirr generation circuit. as noted in ?-9, the mirr signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the mirr comparator level. strictly speaking, however, for mirr to become high, these levels must be compared continuously for a certain time. this sets that time. the preset value is mrc1 = 0, mrc0 = 0. cot2 1 0 0 1 0 stzc hptzc cout cot1 cout pin output * : preset, ? don't care * ? 99 CXD2597Q $3d (preset: $3d 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sfid sfsk thid thsk 0 tld2 tld1 tld0 0 0 0 0 0 0 0 0 sfid: sled servo filter input can be obtained not from sld in reg, but from m0d, which is the trk filter second-stage output. when the low-frequency component of the tracking error signal obtained from the rf amplifier is attenuated, the low frequency can be amplified and input to the sld servo filter. sfsk: only during trk servo gain up2 operation, coefficient k30 is used instead of k00. normally the dc gain between the te input pin and m0d changes for trk filter gain normal and gain up2, and error occurs in the dc level at m0d. in this case, the dc level of the signal transmitted to m00 can be kept uniform by adjusting the k30 value even during the above switching. thid: trk hold filter input can be obtained not from sld in reg, but from m0d, which is the trk filter second-stage output. when signals other than the tracking error signal from the rf amplifier are input to the se input pin, the signal transmitted from the te pin can be obtained as trk hold filter input. thsk: only during trk servo gain up2 operation, coefficient k46 is used instead of k40. normally the dc gain between the te input pin and m0d changes for trk filter gain normal and gain up 2, and error occurs in the dc level at m0d. in this case, the dc level of the signal transmitted to m18 can be kept uniform by adjusting the k46 value even during the above switching. * please refer to ?5-20. filter composition, for further information on sfid, sfsk, thid and thsk commands. tld0 to 2: sld filter correction turns on and off independently of the trk filter. please refer also to $38 (tlc0 to 2) and figure 5-3. tlc0 0 1 0 1 off on off off on on tld0 vc level correction trk filter sld filter * : preset, ?: don't care * tlc1 0 1 0 1 off on off off on on tld1 tracking zero level correction trk filter sld filter * tlc2 0 1 0 1 off on off off on on tld2 traverse center correction trk filter sld filter * ? 100 CXD2597Q input coefficient inversion when sfid = 1 and thid = 1 the preset coefficients for the trk filter are negative for input and positive for output. with this, the CXD2597Q outputs the servo drives which have the reversed phase to the error inputs. t r k f i l t e r n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t e s l d f i l t e r n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t s e t r k h o l d f i l t e r p o s i t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t r k h o l d when sfid = 1, the trk filter negative input coefficient is applied to the sld filter, so invert the sld input coefficient (k00) code. for the same reason, when thid = 1, invert the trk hold input coefficient (k40) code. t r k f i l t e r n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t e s l d f i l t e r p o s i t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t s e t r k h o l d f i l t e r n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t r k h o l d m 0 d please refer also to ?5-20. filter composition. ? 101 CXD2597Q $3e (preset: $3e 00 00) f1nm, f1dm: quasi double accuracy setting for fcs servo filter first-stage on when set to 1; default = 0. f1nm: gain normal f1dm: gain down t1nm, t1um: quasi double accuracy setting for trk servo filter first-stage on when set to 1; default = 0. t1nm: gain normal t1um: gain up f3nm, f3dm: quasi double accuracy setting for fcs servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the fcs servo third-stage filter which is used as the phase compensation filter to double accuracy. f3nm: gain normal f3dm: gain down t3nm, t3um: quasi double accuracy setting for trk servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the trk servo third-stage filter which is used as the phase compensation filter to double accuracy. t3nm: gain normal t3um: gain up note) filter first- and third-stage quasi double accuracy settings can be set individually. see "filter composition" at the end of this specification concerning quasi double accuracy. dfis: fcs hold filter input extraction node selection 0: m05 (data ram address 05); default 1: m04 (data ram address 04) tlcd: this command masks the tlc2 command set by d2 of $38 only when fok is low. on when set to 1; default = 0 lkin: when 0, the internally generated lock signal is output to the lock pin. (default) when 1, the lock signal can be input from an external source to the lock pin. coin: when 0, the internally generated cout signal is output to the cout pin. (default) when 1, the cout signal can be input from an external source to the cout pin. the mirr, dfct and fok signals can also be input from an external source. mdfi: when 0, the mirr, dfct and fok signals are generated internally. (default) when 1, the mirr, dfct and fok signals can be input from an external source through the mirr, dfct and fok pins. miri: when 0, the mirr signal is generated internally. (default) when 1, the mirr signal can be input from an external source through the mirr pin. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f1nm f1dm f3nm f3dm t1nm t1um t3nm t3um dfis tlcd 0 lkin coin mdfi miri xt1d xt1d: the clock input from fsti can be used without being frequency-divided as the master clock for the servo block by setting d0 to 1. this command takes precedence over the xtsl pin, xt2d and xt4d. see the description of $3f for xt2d and xt4d. mdfi 0 0 1 0 1 mirr, dfct and fok are all generated internally. mirr only is input from an external source. mirr, dfct and fok are all input from an external source. miri * * : preset, ? don't care ? 102 CXD2597Q $3f (preset: $3f 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 agg4 xt4d xt2d 0 drr2 drr1 drr0 0 asfg ftq lpas sro1 0 aghf asot xt4d, xt2d: mck (digital servo master clock) frequency division setting this command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when mck is generated from the signal input to the fsti pin. see the description of $3e for xt1d. agg4: this varies the amplitude of the internally generated sine wave using the aggf and aggt commands during agc. when agg4 = 0, the default is used. when agg4 = 1, the setting is as shown in the table below. aggf (msb) 0 0 1 1 0 1 0 1 1/64 v dd 0.4 [v] 1/32 v dd 0.4 1/16 v dd 0.4 1/8 v dd 0.4 aggt (lsb) te/fe input conversion drr2 to drr0: partially clears the data ram values (0 write). the following values are cleared when set to 1 (on) respectively; default = 0 drr2: m08, m09, m0a drr1: m00, m01, m02 drr0: m00, m01, m02 only when lock = low note) set drr1 and drr0 on for 50 s or more. asfg: when vibration detection is performed during anti-shock circuit operation, fcs servo filter is forcibly set to gain normal status. on when set to 1; default = 0 lpas: built-in analog buffer low-current consumption mode this mode reduces the total analog buffer current consumption for the vc, te, se and fe input analog buffers by using a single operational amplifier. on when set to 1; default = 0 note) when using this mode, first check whether each error signal is properly a/d converted using the sro1 and sro0 commands of $3f. sro1: these commands are used to output various data externally continuously which have been specified with the $39 command. (however, d15 (dac) of $39 must be set to 1.) digital output (sock, xolt and sout) can be obtained from three specified pins by setting these commands to 1 respectively. the default is 0, 0. (no readout) the output pins for each case are shown below. sock xolt sout lmut pin wfck pin rmut pin sro1 = 1 (see "description of data readout" on the following page.) aghf: this halves the frequency of the internally generated sine wave during agc. ftq: the slope of the output during focus search is a quarter of the conventional output slope. on when set to 1, default = 0. asot: the anti-shock signal, which is internally detected, is output from the atsk pin. output when set to 1; default = 0. vibration detection when a high signal is output for the anti-shock signal output. these settings are the same for both focus auto gain control and tracking auto gain control. * : preset, ? don't care * xt1d 0 1 0 0 xt2d 0 1 0 xt4d 0 1 according to xtsl 1/1 1/2 1/4 frequency division ratio * * : preset ? 103 CXD2597Q description of data readout s o c k ( 5 . 6 4 4 8 m h z ) x o l t ( 8 8 . 2 k h z ) s o u t m s b l s b m s b l s b 1 6 - b i t r e g i s t e r f o r s e r i a l / p a r a l l e l c o n v e r s i o n 1 6 - b i t r e g i s t e r f o r l a t c h s o u t s o c k x o l t c l k c l k m s b l s b t o t h e 7 - s e g m e n t l e d t o t h e 7 - s e g m e n t l e d d a t a i s c o n n e c t e d t o t h e 7 - s e g m e n t l e d b y 4 - b i t s a t a t i m e . t h i s e n a b l e s h e x d i s p l a y u s i n g f o u r 7 - s e g m e n t l e d s . m s b l s b s o u t s o c k x o l t s e r i a l d a t a i n p u t c l o c k i n p u t l a t c h e n a b l e i n p u t a n a l o g o u t p u t d / a t o a n o s c i l l o s c o p e , e t c . o f f s e t a d j u s t m e n t , g a i n a d j u s t m e n t w a v e f o r m s c a n b e m o n i t o r e d w i t h a n o s c i l l o s c o p e u s i n g a s e r i a l i n p u t - t y p e d / a c o n v e r t e r a s s h o w n a b o v e . ? 104 CXD2597Q ?-19. list of servo filter coefficients ? 105 CXD2597Q ? 106 CXD2597Q ?-20. filter composition the internal filter composition is shown below. k ** and m ** indicate coefficient ram and data ram address values respectively. fcs servo gain normal fs = 88.2khz k 0 d k 0 c k 0 e k 1 0 z 1 k 0 b z 1 k 0 9 k 0 a k 0 8 z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 1 1 k 1 3 k 0 f f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 a g f o n k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g s i n r o m fcs servo gain down fs = 88.2khz k 2 9 k 2 8 k 2 a k 2 c z 1 k 2 7 z 1 k 2 5 k 2 6 k 2 4 z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 2 d k 1 3 k 2 b f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g note) set the msb bit of the k0b and k0d coefficients to 0. note) set the msb bit of the k27 and k29 coefficients to 0. ? 107 CXD2597Q trk servo gain normal fs = 88.2khz k 1 f k 1 e k 2 0 k 2 1 z 1 k 1 d z 1 k 1 b k 1 c k 1 a z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 2 2 k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 a g t o n k 1 9 d f c t t r k h o l d r e g t r k i n r e g s i n r o m t o s l d s e r v o , t r k h o l d note) set the msb bit of the k1d and k1f coefficients to 0. trk servo gain up 1 fs = 88.2khz k 3 d z 1 z 1 k 1 b k 3 c k 1 a z 1 m 0 c m 0 b m 0 e k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g ? 108 CXD2597Q trk servo gain up 2 fs = 88.2khz k 3 b k 3 a k 3 c k 3 d z 1 k 3 9 z 1 k 3 7 k 3 8 k 3 6 z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g t o s l d s e r v o , t r k h o l d note) set the msb bit of the k39 and k3b coefficients to 0. sld servo fs = 345hz k 0 4 k 0 3 z 1 k 0 2 z 1 k 0 1 k 0 0 m 0 0 2 7 2 7 m 0 1 k 0 5 k 0 7 t r k a u t o g a i n s l d p w m 2 7 s l d m o v m 0 2 s l d i n r e g 2 1 k 3 0 s f s k ( o n l y w h e n t g u p 2 i s u s e d ) s f i d m 0 d t r k s e r v o f i l t e r s e c o n d - s t a g e o u t p u t note) set the msb bit of the k02 and k04 coefficients to 0. hptzc/auto gain fs = 88.2khz k 1 5 k 1 7 z 1 k 1 4 m 0 8 m 0 9 m 0 a z 1 a u t o g a i n r e g 2 1 a g t o n a g f o n a g f o n f c s i n r e g t r k i n r e g s i n r o m z 1 s l i c e t z c r e g s l i c e 2 1 ? 109 CXD2597Q anti shock fs = 88.2khz k 3 4 k 3 3 z 1 z 1 k 3 1 k 1 6 z 1 m 0 9 m 0 8 2 7 m 0 a k 3 5 c o m p k 1 2 a n t i s h o c k r e g 2 1 t r k i n r e g note) set the msb bit of the k34 coefficient to 0. the comparator input is 1/16 the maximum amplitude of the comparator input. avrg fs = 88.2khz m 0 8 a v r g r e g 2 1 v c , t e , f e , r f d c z 1 2 7 trk hold fs = 345hz k 4 4 k 4 3 z 1 k 4 2 z 1 k 4 1 k 4 0 m 1 8 2 7 2 7 m 1 9 k 4 5 t r k h o l d r e g s l d i n r e g 2 1 k 4 6 t h s k ( o n l y w h e n t g u p 2 i s u s e d ) t h i d m 0 d t r k s e r v o f i l t e r s e c o n d - s t a g e o u t p u t note) set the msb bit of the k42 and k44 coefficients to 0. fcs hold fs = 345hz k 4 c k 4 b z 1 k 4 a z 1 k 4 9 k 4 8 m 1 0 2 7 2 7 m 1 1 k 4 d f c s h o l d r e g 1 f c s h o l d r e g 2 note) set the msb bit of the k4a and k4c coefficients to 0. ? 110 CXD2597Q fcs servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3eaxx0) k 0 d k 0 c 8 0 h k 1 0 z 1 k 0 b z 1 7 f h k 0 a 8 1 h z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 1 1 k 1 3 k 0 f f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 a g f o n k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g s i n r o m k 0 8 k 0 9 2 7 2 7 k 0 e 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k0b and k0d coefficients during normal operation, and of the k08, k09 and k0e coefficients during quasi double accuracy to 0. fcs servo gain down; fs = 88.2khz, during quasi double accuracy (ex.: $3e5xx0) k 2 9 k 2 8 8 0 h k 2 c z 1 k 2 7 z 1 7 f h k 2 6 8 1 h z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 2 d k 1 3 k 2 b f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g k 2 4 k 2 5 2 7 2 7 k 2 a 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k27 and k29 coefficients during normal operation, and of the k24, k25 and k2a coefficients during quasi double accuracy to 0. ? 111 CXD2597Q trk servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3exax0) k 1 f k 1 e 8 0 h k 2 1 z 1 k 1 d z 1 7 f h k 1 c 8 1 h z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 2 2 k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 a g t o n k 1 9 d f c t t r k h o l d r e g t r k i n r e g s i n r o m k 1 a k 1 b 2 7 2 7 k 2 0 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1d and k1f coefficients during normal operation, and of the k1a, k1b and k20 coefficients during quasi double accuracy to 0. trk servo gain up 1; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k 3 d z 1 k 3 c z 1 7 f h 8 0 h 8 1 h z 1 m 0 c m 0 b 2 7 m 0 e k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g k 1 a k 1 b 2 7 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1a, k1b and k3c coefficients during quasi double accuracy to 0. ? 112 CXD2597Q trk servo gain up 2; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k 3 b k 3 a 8 0 h k 3 d z 1 k 3 9 z 1 7 f h k 3 8 8 1 h z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g k 3 6 k 3 7 2 7 2 7 k 3 c 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k39 and k3b coefficients during normal operation, and of the k36, k37 and k3c coefficients during quasi double accuracy to 0. ? 113 CXD2597Q ?-21. tracking and focus frequency response 2 0 k 1 k 1 0 0 1 0 2 . 1 g 2 0 k 1 k 1 0 0 1 0 2 . 1 g f f r e q u e n c y [ h z ] 1 0 0 1 0 2 0 3 0 4 0 g g a i n [ d b ] 1 8 0 f p h a s e [ d e g r e e ] 0 1 8 0 9 0 9 0 f f r e q u e n c y [ h z ] 1 0 0 1 0 2 0 3 0 4 0 g g a i n [ d b ] 1 8 0 f p h a s e [ d e g r e e ] 0 1 8 0 9 0 9 0 t r a c k i n g f r e q u e n c y r e s p o n s e f o c u s f r e q u e n c y r e s p o n s e f f n o r m a l g a i n u p n o r m a l g a i n d o w n ? 114 CXD2597Q 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 l r c k p c m d b c k e m p h x v d d x t a i x t a o x v s s a v d d 1 a o u t 1 a i n 1 l o u t 1 a v s s 1 a v s s 2 l o u t 2 a i n 2 a o u t 2 a v d d 2 r m u t l m u t s e f e v c x t s l t e s 1 t e s t v s s f r d r c o u t f f d r t r d r t f d r s r d r s f d r s s t p m d p l o c k m i r r d o u t v d d v s s f i l i t e r f d c a v d d 3 p c o f i l o a v s s 3 a s y o a v d d 0 i g e n a v s s 0 b i a s a s y i r f a c s q c k x l a t s e n s d a t a x r s t s y s m c l o k v d d s q s o s c l k s c o r a t s k s p o a s p o b x l o n w f c k x u g f x p c k g f s c 2 p o f o k d f c t x r s t s q c k m u t e x l a t d a t a c l o k s e n s s c l k g f s s c o r f o k v d d g n d s q s o l d o n x l o n w f c k x u g f x p c k c 2 p o l r c k p c m d b c k e m p h r m u t l m u t d o u t c o u t l o c k m i r r d f c t d r i v e r c i r c u i t t g t d f d v c c l d o n g n d r f o f z c f e t e c e f g v c s l e d s s t p s p d l g n d + 5 v c l t v v c t l v p c o ?. application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ? 115 CXD2597Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y q f p - 8 0 p - l 0 3 q f p 0 8 0 - p - 1 4 1 4 0 . 6 g 8 0 p i n q f p ( p l a s t i c ) 1 6 . 0 0 . 4 1 4 . 0 0 . 1 + 0 . 4 0 . 3 0 . 1 + 0 . 1 5 0 t o 1 0 0 . 5 0 . 2 0 . 1 0 . 1 + 0 . 1 5 ( 1 5 . 0 ) 0 . 1 2 7 0 . 0 5 + 0 . 1 1 . 5 0 . 1 5 + 0 . 3 5 4 0 2 1 2 0 1 4 1 6 0 6 1 8 0 m 0 . 2 4 0 . 1 0 . 6 5 |
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